Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.
The following table summarizes the configurations to be supported by the P-Tile Avalon® -MM design examples:
Table 1. Configurations Supported by the P-Tile Avalon® -MM Design Examples
|Root Port (RP)
Note: Gen1/Gen2 x1/x2 configurations are supported via link down-training.
Note: N/A = configuration not supported.
In the available design example, the only active blocks within the P-Tile Avalon®
-MM IP for PCIe are the Data Movers.