1. Design Example Overview 2. Endpoint Design Example 3. Current Limitations of the Design Examples 4. Quick Start Guide 5. P-Tile Avalon Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide Archives A. Document Revision History for the P-Tile Avalon® Memory-mapped Intel FPGA IP for PCI Express Design Example User Guide
1. Design Example Overview
|Intel® Quartus® Prime Design Suite 21.1|
|IP Version 4.0.0|
Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.
The following table summarizes the configurations to be supported by the P-Tile Avalon® -MM design examples:
Note: Gen1/Gen2 x1/x2 configurations are supported via link down-training.
Note: N/A = configuration not supported.
1 In the available design example, the only active blocks within the P-Tile Avalon® -MM IP for PCIe are the Data Movers.
2 A design example supporting these configurations may be available in a future release of Intel® Quartus® Prime.