P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* Design Example User Guide

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ID 683853
Date 3/28/2022
Public

1. Design Example Overview

Updated for:
Intel® Quartus® Prime Design Suite 21.1
IP Version 4.0.0
Note: Do not use the P-tile Avalon® Memory-mapped IP for PCI Express* for new designs. This IP will not be available in future releases of Intel® Quartus® Prime. For new designs, use the Multi-Channel DMA IP.

The following table summarizes the configurations to be supported by the P-Tile Avalon® -MM design examples:

Table 1.  Configurations Supported by the P-Tile Avalon® -MM Design Examples
  Gen3/Gen4 x16 Gen3/Gen4 x8 Gen3/Gen4 x4
Endpoint (EP) Yes 1 Yes N/A
Root Port (RP) 2 N/A 2
Note: Gen1/Gen2 x1/x2 configurations are supported via link down-training.
Note: N/A = configuration not supported.
1 In the available design example, the only active blocks within the P-Tile Avalon® -MM IP for PCIe are the Data Movers.
2 A design example supporting these configurations may be available in a future release of Intel® Quartus® Prime.

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