8.3. Recommended Reset Sequence to Avoid Link Training Issues
- Wait until the FPGA is configured as indicated by the assertion of CONFIG_DONE from the FPGA block controller.
- Deassert the mgmt_rst_reset input to the Transceiver Reconfiguration Controller IP Core.
- Wait for tx_cal_busy and rx_cal_busy SERDES outputs to be deasserted.
Deassert pin_perstn to take the Hard IP for PCIe out of reset. For plug-in cards, the minimum assertion time for pin_perstn is 100 ms. Embedded systems do not have a minimum assertion time for pin_perstn.
- Wait for thereset_status output to be deasserted
- Deassert the reset output to the Application Layer.
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