2.2. Generating the Example Design
- On the Generate menu, select Generate Testbench System. The Generation dialog box appears.
- Under Testbench System, set the following options:
- For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.
- For Create testbench simulation model, select Verilog.
- You can retain the default values for all other parameters.
- Click Generate.
- After Qsys reports Generation Completed, click Close.
- On the File menu, click Save.
The following table lists the testbench and simulation directories Qsys generates.
The design example simulation includes the following components and software:
- The Qsys system
- A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g1x4_tb.qsys.
- The ModelSim software
Complete the following steps to run the Qsys testbench:
- In a terminal window, change to the <project_dir>/ep_g1x4/testbench/mentor directory.
- Start the ModelSim® simulator.
- Type the following commands in a terminal window:
- do msim_setup.tcl
- run 140000 ns
The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:
- Various configuration accesses to the Avalon‑MM Arria V Hard IP for PCI Express in your system after the link is initialized
- Setup of the Address Translation Table for requests that are coming from the DMA component
- Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared memory
- Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory
- Data comparison and report of any mismatch
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