Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Document Table of Contents

2.2. Generating the Example Design

  1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.
  2. Under Testbench System, set the following options:
    1. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.
    2. For Create testbench simulation model, select Verilog.
  3. You can retain the default values for all other parameters.
  4. Click Generate.
  5. After Qsys reports Generation Completed, click Close.
  6. On the File menu, click Save.

The following table lists the testbench and simulation directories Qsys generates.

Table 8.  Qsys System Generated Directories



Qsys system




Simulation Model


The design example simulation includes the following components and software:

  • The Qsys system
  • A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g1x4_tb.qsys.
  • The ModelSim software
Note: You can also use any other supported third-party simulator to simulate your design.

Complete the following steps to run the Qsys testbench:

  1. In a terminal window, change to the <project_dir>/ep_g1x4/testbench/mentor directory.
  2. Start the ModelSim® simulator.
  3. Type the following commands in a terminal window:
    1. do msim_setup.tcl
    2. ld_debug
    3. run 140000 ns

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

  1. Various configuration accesses to the Avalon‑MM Arria V Hard IP for PCI Express in your system after the link is initialized
  2. Setup of the Address Translation Table for requests that are coming from the DMA component
  3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared memory
  4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory
  5. Data comparison and report of any mismatch

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