Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Public
Document Table of Contents
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4.6.3.2. Channel Placement in Arria V Devices

Figure 18.  Arria V Gen1 and Gen2 Channel Placement Using the CMU PLLIn the following figures the channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock.

You can assign other protocols to unused channels the if data rate and clock specification exactly match the PCIe configuration.