Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Document Table of Contents

1.1. Avalon-MM Interface for PCIe Datasheet

Intel® Arria® V FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express PCIe* IP core using the Avalon® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in FPGA soft logic. It is available in Qsys. The following figure shows the high-level modules and connecting interfaces for this variant.

Figure 1.  Arria V PCIe Variant with Avalon-MM Interface
Table 1.  PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5 giga-transfers per second for Gen2. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

Link Width in Gigabits Per Second (Gbps)
×1 ×2 ×4 ×8

PCI Express Gen1 (2.5 Gbps)





PCI Express Gen2 (5.0 Gbps)





Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs.

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