Arria® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions: User Guide

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ID 683773
Date 10/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Arria V Devices 4.6.3.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

1.1. Avalon-MM Interface for PCIe Datasheet

Intel® Arria® V FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express PCIe* IP core using the Avalon® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in FPGA soft logic. It is available in Platform Designer. The following figure shows the high-level modules and connecting interfaces for this variant.

Figure 1.  Arria V PCIe Variant with Avalon-MM Interface
Table 1.  PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5 giga-transfers per second for Gen2. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

Link Width in Gigabits Per Second (Gbps)
×1 ×2 ×4 ×8

PCI Express Gen1 (2.5 Gbps)

2

4

8

16

PCI Express Gen2 (5.0 Gbps)

4

8

16

N/A

Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Intel FPGAs.

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