Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Public
Document Table of Contents

1.2. Features

The Arria® V Hard IP for PCI Express with the Avalon-MM interface supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • Support for ×1, ×2, and ×4 configurations with Gen1 and Gen2 Root Ports and Endpoints. Support for the ×8 configuration for Gen1 Root Ports and Endpoints.
  • Dedicated 16 kilobyte (KB) receive buffer.
  • Optional hard reset controller for Gen2.
  • Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
  • Qsys example designs demonstrating parameterization, design modules, and connectivity.
  • Extended credit allocation settings to better optimize the RX buffer space based on application type.
  • Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

    Easy to use:
    • Flexible configuration.
    • No license requirement.
    • Example designs to get started.
Table 2.  Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.

Feature

Avalon‑ST Interface

Avalon‑MM Interface

Avalon‑MM DMA

IP Core License

Free

Free

Free

Native Endpoint

Supported

Supported

Supported

Legacy Endpoint 1

Supported

Not Supported

Not Supported

Root port

Supported

Supported

Not Supported

Gen1

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

x8

Gen2

×1, ×2, ×4

×1, ×2, ×4

×4

64-bit Application Layer interface

Supported

Supported

Not supported

128-bit Application Layer interface

Supported

Supported

Supported

Transaction Layer Packet type (TLP) 

  • Memory Read Request
  • Memory Read Request-Locked
  • Memory Write Request
  • I/O Read Request
  • I/O Write Request
  • Configuration Read Request (Root Port)
  • Configuration Write Request (Root Port)
  • Message Request
  • Message Request with Data Payload
  • Completion Message
  • Completion with Data
  • Completion for Locked Read without Data
  • Memory Read Request
  • Memory Write Request
  • I/O Read Request—Root Port only
  • I/O Write Request—Root Port only
  • Configuration Read Request (Root Port)
  • Configuration Write Request (Root Port)
  • Completion Message
  • Completion with Data
  • Memory Read Request (single dword)
  • Memory Write Request (single dword)
  • Memory Read Request
  • Memory Write Request
  • Completion Message
  • Completion with Data

Payload size

128–512 bytes

128 or 256 bytes

128 or 256 bytes

Number of tags supported for non-posted requests

32 or 64

8 for 64-bit interface

16 for 128-bit interface

16

62.5 MHz clock

Supported

Supported

Not Supported

Multi-function

Supports up to 8 functions

Supports single function only

Supports single function only

Out‑of‑order completions (transparent to the Application Layer)

Not supported

Supported

Supported

Requests that cross 4 KB address boundary (transparent to the Application Layer)

Not supported

Supported

Supported

Polarity Inversion of PIPE interface signals

Supported

Supported

Supported

ECRC forwarding on RX and TX

Supported

Not supported

Not supported

Number of MSI requests

1, 2, 4, 8, or 16

1, 2, 4, 8, or 16

1, 2, 4, 8, or 16

MSI-X

Supported

Supported

Supported

Legacy interrupts

Supported

Supported

Supported

Expansion ROM

Supported

Not supported

Not supported

PCIe bifurcation Not supported Not supported Not supported
Table 3.  TLP Support Comparison for all Hard IP for PCI Express IP CoresThe table compares the TLP types that the variants of the Hard IP for PCI Express IP Cores can transmit. Each entry indicates whether this TLP type is supported (for transmit) by Endpoints (EP), Root Ports (RP), or both (EP/RP).

Transaction Layer Packet type (TLP) (transmit support)

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Memory Read Request (Mrd) EP/RP EP/RP EP
Memory Read Lock Request (MRdLk) EP/RP   EP
Memory Write Request (MWr) EP/RP EP/RP EP
I/O Read Request (IORd) EP/RP EP/RP  
I/O Write Request (IOWr) EP/RP EP/RP  
Config Type 0 Read Request (CfgRd0) RP RP  
Config Type 0 Write Request (CfgWr0) RP RP  
Config Type 1 Read Request (CfgRd1) RP RP  
Config Type 1 Write Request (CfgWr1) RP RP  
Message Request (Msg) EP/RP EP/RP  
Message Request with Data (MsgD) EP/RP EP/RP  
Completion (Cpl) EP/RP EP/RP EP
Completion with Data (CplD) EP/RP EP/RP EP
Completion-Locked (CplLk) EP/RP    
Completion Lock with Data (CplDLk) EP/RP    
Fetch and Add AtomicOp Request (FetchAdd) EP    

The purpose of the Arria VAvalon-MM Interface for PCIe Solutions User Guide is to explain how to use this IP core and not to explain the PCI Express protocol. Although there is inevitable overlap between these two purposes, this document should be used in conjunction with an understanding of the PCI Express Base Specification.

Note: This release provides separate user guides for the different variants. The Related Information provides links to all versions.
1 Not recommended for new designs.

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