Arria V Avalon-MM Interface for PCIe Solutions: User Guide

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ID 683773
Date 5/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Design Implementation 9. Additional Features 10. Transceiver PHY IP Reconfiguration 11. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Arria V Devices 4.6.3.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Design Implementation x
8.1. Making Analog QSF Assignments Using the Assignment Editor 8.2. Making Pin Assignments 8.3. Recommended Reset Sequence to Avoid Link Training Issues
9. Additional Features x
9.1. Configuration over Protocol (CvP) 9.2. Autonomous Mode 9.3. ECRC
9.2. Autonomous Mode x
9.2.1. Enabling Autonomous Mode 9.2.2. Enabling CvP Initialization
9.3. ECRC x
9.3.1. ECRC on the RX Path 9.3.2. ECRC on the TX Path
10. Transceiver PHY IP Reconfiguration x
10.1. Connecting the Transceiver Reconfiguration Controller IP Core 10.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
11. Debugging x
11.1. Hardware Bring-Up Issues 11.2. Link Training 11.3. Use Third-Party PCIe Analyzer 11.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Design Implementation
9. Additional Features
10. Transceiver PHY IP Reconfiguration
11. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

1.2. Features

The Arria® V Hard IP for PCI Express with the Avalon-MM interface supports the following features:

  • Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as hard IP.
  • Support for ×1, ×2, and ×4 configurations with Gen1 and Gen2 Root Ports and Endpoints. Support for the ×8 configuration for Gen1 Root Ports and Endpoints.
  • Dedicated 16 kilobyte (KB) receive buffer.
  • Optional hard reset controller for Gen2.
  • Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core bitstreams to be stored separately.
  • Qsys example designs demonstrating parameterization, design modules, and connectivity.
  • Extended credit allocation settings to better optimize the RX buffer space based on application type.

  • Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error reporting (AER) for high reliability applications.

    Easy to use:
    • Flexible configuration.
    • No license requirement.
    • Example designs to get started.
Table 2.  Feature Comparison for all Hard IP for PCI Express IP CoresThe table compares the features of the four Hard IP for PCI Express IP Cores.

Feature

Avalon‑ST Interface

Avalon‑MM Interface

Avalon‑MM DMA

IP Core License

Free

Free

Free

Native Endpoint

Supported

Supported

Supported

Legacy Endpoint 1

Supported

Not Supported

Not Supported

Root port

Supported

Supported

Not Supported

Gen1

×1, ×2, ×4, ×8

×1, ×2, ×4, ×8

x8

Gen2

×1, ×2, ×4

×1, ×2, ×4

×4

64-bit Application Layer interface

Supported

Supported

Not supported

128-bit Application Layer interface

Supported

Supported

Supported

Transaction Layer Packet type (TLP) 

  • Memory Read Request
  • Memory Read Request-Locked
  • Memory Write Request
  • I/O Read Request
  • I/O Write Request
  • Configuration Read Request (Root Port)
  • Configuration Write Request (Root Port)
  • Message Request
  • Message Request with Data Payload
  • Completion Message
  • Completion with Data
  • Completion for Locked Read without Data
  • Memory Read Request
  • Memory Write Request
  • I/O Read Request—Root Port only
  • I/O Write Request—Root Port only
  • Configuration Read Request (Root Port)
  • Configuration Write Request (Root Port)
  • Completion Message
  • Completion with Data
  • Memory Read Request (single dword)
  • Memory Write Request (single dword)
  • Memory Read Request
  • Memory Write Request
  • Completion Message
  • Completion with Data

Payload size

128–512 bytes

128 or 256 bytes

128 or 256 bytes

Number of tags supported for non-posted requests

32 or 64

8 for 64-bit interface

16 for 128-bit interface

16

62.5 MHz clock

Supported

Supported

Not Supported

Multi-function

Supports up to 8 functions

Supports single function only

Supports single function only

Out‑of‑order completions (transparent to the Application Layer)

Not supported

Supported

Supported

Requests that cross 4 KB address boundary (transparent to the Application Layer)

Not supported

Supported

Supported

Polarity Inversion of PIPE interface signals

Supported

Supported

Supported

ECRC forwarding on RX and TX

Supported

Not supported

Not supported

Number of MSI requests

1, 2, 4, 8, or 16

1, 2, 4, 8, or 16

1, 2, 4, 8, or 16

MSI-X

Supported

Supported

Supported

Legacy interrupts

Supported

Supported

Supported

Expansion ROM

Supported

Not supported

Not supported

PCIe bifurcation Not supported Not supported Not supported
Table 3.  TLP Support Comparison for all Hard IP for PCI Express IP CoresThe table compares the TLP types that the variants of the Hard IP for PCI Express IP Cores can transmit. Each entry indicates whether this TLP type is supported (for transmit) by Endpoints (EP), Root Ports (RP), or both (EP/RP).

Transaction Layer Packet type (TLP) (transmit support)

Avalon-ST Interface

Avalon-MM Interface

Avalon-MM DMA

Memory Read Request (Mrd) EP/RP EP/RP EP
Memory Read Lock Request (MRdLk) EP/RP   EP
Memory Write Request (MWr) EP/RP EP/RP EP
I/O Read Request (IORd) EP/RP EP/RP  
I/O Write Request (IOWr) EP/RP EP/RP  
Config Type 0 Read Request (CfgRd0) RP RP  
Config Type 0 Write Request (CfgWr0) RP RP  
Config Type 1 Read Request (CfgRd1) RP RP  
Config Type 1 Write Request (CfgWr1) RP RP  
Message Request (Msg) EP/RP EP/RP  
Message Request with Data (MsgD) EP/RP EP/RP  
Completion (Cpl) EP/RP EP/RP EP
Completion with Data (CplD) EP/RP EP/RP EP
Completion-Locked (CplLk) EP/RP    
Completion Lock with Data (CplDLk) EP/RP    
Fetch and Add AtomicOp Request (FetchAdd) EP    

The purpose of the Arria VAvalon-MM Interface for PCIe Solutions User Guide is to explain how to use this IP core and not to explain the PCI Express protocol. Although there is inevitable overlap between these two purposes, this document should be used in conjunction with an understanding of the PCI Express Base Specification.

Note: This release provides separate user guides for the different variants. The Related Information provides links to all versions.
Related Information
1 Not recommended for new designs.
Level Two Title