Arria® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions: User Guide

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ID 683773
Date 10/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Arria V Devices 4.6.3.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port

Table 57.  Configuration Space Register Descriptions For registers that are less than 32 bits, the upper bits are unused.
Byte Offset

Register

Dir

Description

14'h3C00 cfg_dev_ctrl[15:0]

O

cfg_devctrl[15:0] is device control for the PCI Express capability structure.

14'h3C04 cfg_dev_ctrl2[15:0]

O

cfg_dev2ctrl[15:0] is device control 2 for the PCI Express capability structure.

14'h3C08 cfg_link_ctrl[15:0]

O

cfg_link_ctrl[15:0]is the primary Link Control of the PCI Express capability structure.

For Gen2 or Gen3 operation, you must write a 1’b1 to Retrain Link bit (Bit[5] of the cfg_link_ctrl) of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Arria V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

14'h3C0C cfg_link_ctrl2[15:0]

O

cfg_link_ctrl2[31:16] is the secondary Link Control register of the PCI Express capability structure for Gen2 operation.

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

14'h3C10 cfg_prm_cmd[15:0]

O

Base/Primary Command register for the PCI Configuration Space.

14'h3C14 cfg_root_ctrl[7:0]

O

Root control and status register of the PCI-Express capability. This register is only available in Root Port mode.

14'h3C18 cfg_sec_ctrl[15:0]

O

Secondary bus Control and Status register of the PCI-Express capability. This register is only available in Root Port mode.

14'h3C1C cfg_secbus[7:0]

O

Secondary bus number. Available in Root Port mode.

14'h3C20 cfg_subbus[7:0]

O

Subordinate bus number. Available in Root Port mode.

14'h3C24 cfg_msi_addr_low[31:0]

O

cfg_msi_add[31:0] is the MSI message address.

14'h3C28 cfg_msi_addr_hi[63:32]

O

cfg_msi_add[63:32] is the MSI upper message address.

14'h3C2C cfg_io_bas[19:0]

O

The IO base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C30 cfg_io_lim[19:0]

O

The IO limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C34 cfg_np_bas[11:0]

O

The non-prefetchable memory base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C38 cfg_np_lim[11:0]

O

The non-prefetchable memory limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C3C cfg_pr_bas_low[31:0]

O

The lower 32 bits of the prefetchable base register of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C40 cfg_pr_bas_hi[43:32]

O

The upper 12 bits of the prefetchable base registers of the Type1 Configuration Space. This register is only available in Root Port mode.

14'h3C44 cfg_pr_lim_low[31:0]

O

The lower 32 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

14'h3C48 cfg_pr_lim_hi[43:32]

O

The upper 12 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

14'h3C4C cfg_pmcsr[31:0]

O

cfg_pmcsr[31:16] is Power Management Control and cfg_pmcsr[15:0]is the Power Management Status register.

14'h3C50 cfg_msixcsr[15:0]

O

MSI-X message control register.

14'h3C54 cfg_msicsr[15:0]

O

MSI message control.

14'h3C58 cfg_tcvcmap[23:0]

O

Configuration traffic class (TC)/virtual channel (VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

The following encodings are defined:
  • cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
  • cfg_tcvcmap[5:3]: Mapping for TC1.
  • cfg_tcvcmap[8:6]: Mapping for TC2.
  • cfg_tcvcmap[11:9]: Mapping for TC3.
  • cfg_tcvcmap[14:12]: Mapping for TC4.
  • cfg_tcvcmap[17:15]: Mapping for TC5.
  • cfg_tcvcmap[20:18]: Mapping for TC6.
  • cfg_tcvcmap[23:21]: Mapping for TC7.
14'h3C5C cfg_msi_data[15:0]

O

cfg_msi_data[15:0] is message data for MSI.

14'h3C60 cfg_busdev[12:0]

O

Bus/Device Number captured by or programmed in the Hard IP.

14'h3C64 ltssm_reg[4:0]

O

Specifies the current LTSSM state. The LTSSM state machine encoding defines the following states:
  • 00000: Detect.Quiet
  • 00001: Detect.Active
  • 00010: Polling.Active
  • 00011: Polling.Compliance
  • 00100: Polling.Configuration
  • 00101: Polling.Speed
  • 00110: config.Linkwidthstart
  • 00111: Config.Linkaccept
  • 01000: Config.Lanenumaccept
  • 01001: Config.Lanenumwait
  • 01010: Config.Complete
  • 01011: Config.Idle
  • 01100: Recovery.Rcvlock
  • 01101: Recovery.Rcvconfig
  • 01110: Recovery.Idle
  • 01111: L0
  • 10000: Disable
  • 10001: Loopback.Entry
  • 10010: Loopback.Active
  • 10011: Loopback.Exit
  • 10100: Hot.Reset
  • 10101: LOs
  • 11001: L2.transmit.Wake
  • 11010: Recovery.Speed
  • 11011: Recovery.Equalization, Phase 0
  • 11100: Recovery.Equalization, Phase 1
  • 11101: Recovery.Equalization, Phase 2
  • 11110: recovery.Equalization, Phase 3
14'h3C68 current_speed_reg[1:0]

O

Indicates the current speed of the PCIe link. The following encodings are defined:

  • 2b’00: Undefined
  • 2b’01: Gen1
  • 2b’10: Gen2
  • 2b’11: Gen3
14'h3C6C lane_act_reg[3:0]

O

Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:

  • 4’b0001: 1 lane
  • 4’b0010: 2 lanes
  • 4’b0100: 4 lanes
  • 4’b1000: 8 lanes
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