The Avalon-MM Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:
- Physical (PHY), including:
- Physical Media Attachment (PMA)
- Physical Coding Sublayer (PCS)
- Media Access Control (MAC)
- Data Link Layer (DL)
- Transaction Layer (TL)
When configured as an Endpoint, the Arria V Hard IP for PCI Express using the Avalon-MM supports memory read and write requests and completions with or without data.
- A Root Port that connects directly to a second FPGA that includes an Endpoint.
- Two Endpoints that connect to a PCIe switch.
- A host CPU that implements CvP using the PCI Express link connects through the switch. For more information about configuration over a PCI Express link below.
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