Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Public
Document Table of Contents

4.6.3.1. Physical Layout of Hard IP in Arria V Devices

/>Arria V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate the placement of the PCIe IP cores, transceiver banks, and channels. Note that the bottom left IP core includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality.

Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files for Intel Devices.

Figure 16.  Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria® V GX and GT Devices
Figure 17.  Arria V Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria® V SX and ST Devices

Channel utilization for x1, x2, x4, and x8 variants is as follows:

Table 32.  Channel Utilization
Variant Data CMU Clock
x1, 1 instance Channel 0 of GXB_L0 Channel 1 of GXB_L0
x1, 2 instances Channel 0 of GXB_L0, Channel 0 of GXB_R0 Channel 1 of GXB_L0, Channel 1 of GXB_R0
x2, 1 instance Channels 1–2 of GXB_L0 Channel 4 of GXB_L0
x2, 2 instances Channels 1–2 of GXB_L0, Channels 1–2 of GXB_R0 Channel 4 of GXB_L0, Channel 4 of GXB_R0
x4, 1 instance Channels 0–3 of GXB_L0 Channel 4 of GXB_L0
x4, 2 instances Channels 0–3 of GXB_L0, Channels 0–3 of GXB_R0 Channel 4 of GXB_L0, Channel 4 of GXB_R0
x8, 1 instance Channels 0–3 and 5 of GXB_L0 and channels 0-2 of GXB_L1 Channel 4 of GXB_L0

Did you find the information on this page useful?

Characters remaining:

Feedback Message