Arria® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions: User Guide

Download PDF
ID 683773
Date 10/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Arria V Devices 4.6.3.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

5.1. Correspondence between Configuration Space Registers and the PCIe Specification

Table 35.  Address Map of Hard IP Configuration Space RegistersFor the Type 0 and Type 1 Configuration Space Headers, the first line of each entry lists Type 0 values and the second line lists Type 1 values when the values differ.

Byte Address

Hard IP Configuration Space Register

Corresponding Section in PCIe Specification

0x000:0x03C

PCI Header Type 0 Configuration Registers

Type 0 Configuration Space Header

0x000:0x03C

PCI Header Type 1 Configuration Registers

Type 1 Configuration Space Header

0x040:0x04C

Reserved

N/A

0x050:0x05C

MSI Capability Structure

MSI Capability Structure

0x068:0x070

MSI-X Capability Structure

MSI-X Capability Structure

0x070:0x074

Reserved

N/A

0x078:0x07C

Power Management Capability Structure

PCI Power Management Capability Structure

0x080:0x0BC

PCI Express Capability Structure

PCI Express Capability Structure

0x0C0:0x0FC

Reserved

N/A

0x100:0x16C

Virtual Channel Capability Structure

Virtual Channel Capability

0x170:0x17C

Reserved

N/A

0x180:0x1FC

Virtual channel arbitration table

VC Arbitration Table

0x200:0x23C

Port VC0 arbitration table

Port Arbitration Table

0x240:0x27C

Port VC1 arbitration table

Port Arbitration Table

0x280:0x2BC

Port VC2 arbitration table

Port Arbitration Table

0x2C0:0x2FC

Port VC3 arbitration table

Port Arbitration Table

0x300:0x33C

Port VC4 arbitration table

Port Arbitration Table

0x340:0x37C

Port VC5 arbitration table

Port Arbitration Table

0x380:0x3BC

Port VC6 arbitration table

Port Arbitration Table

0x3C0:0x3FC

Port VC7 arbitration table

Port Arbitration Table

0x400:0x7FC

Reserved

PCIe spec corresponding section name

0x800:0x834

Advanced Error Reporting AER (optional)

Advanced Error Reporting Capability

0x838:0xFFF

Reserved

N/A

Overview of Configuration Space Register Fields

0x000

Device ID, Vendor ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x004

Status, Command

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x008

Class Code, Revision ID

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x00C

BIST, Header Type, Primary Latency Timer, Cache Line Size

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x010

Base Address 0

Base Address Registers

0x014

Base Address 1

Base Address Registers

0x018

Base Address 2

Secondary Latency Timer, Subordinate Bus Number, Secondary Bus Number, Primary Bus Number

Base Address Registers

Secondary Latency Timer, Type 1 Configuration Space Header, Primary Bus Number

0x01C

Base Address 3

Secondary Status, I/O Limit, I/O Base

Base Address Registers

Secondary Status Register ,Type 1 Configuration Space Header

0x020

Base Address 4

Memory Limit, Memory Base

Base Address Registers

Type 1 Configuration Space Header

0x024

Base Address 5

Prefetchable Memory Limit, Prefetchable Memory Base

Base Address Registers

Prefetchable Memory Limit, Prefetchable Memory Base

0x028

Reserved

Prefetchable Base Upper 32 Bits

N/A

Type 1 Configuration Space Header

0x02C

Subsystem ID, Subsystem Vendor ID

Prefetchable Limit Upper 32 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x030

I/O Limit Upper 16 Bits, I/O Base Upper 16 Bits

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x034

Reserved, Capabilities PTR

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x038

Reserved

N/A

0x03C

Interrupt Pin, Interrupt Line

Bridge Control, Interrupt Pin, Interrupt Line

Type 0 Configuration Space Header

Type 1 Configuration Space Header

0x050

MSI-Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x054

Message Address

MSI and MSI-X Capability Structures

0x058

Message Upper Address

MSI and MSI-X Capability Structures

0x05C

Reserved Message Data

MSI and MSI-X Capability Structures

0x068

MSI-X Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x06C

MSI-X Table Offset BIR

MSI and MSI-X Capability Structures

0x070

Pending Bit Array (PBA) Offset BIR

MSI and MSI-X Capability Structures

0x078

Capabilities Register Next Cap PTR Cap ID

PCI Power Management Capability Structure

0x07C

Data PM Control/Status Bridge Extensions Power Management Status & Control

PCI Power Management Capability Structure

0x080

PCI Express Capabilities Register Next Cap Ptr PCI Express Cap ID

PCI Express Capability Structure

0x084

Device Capabilities Register

PCI Express Capability Structure

0x088

Device Status Register Device Control Register

PCI Express Capability Structure

0x08C

Link Capabilities Register

PCI Express Capability Structure

0x090

Link Status Register Link Control Register

PCI Express Capability Structure

0x094

Slot Capabilities Register

PCI Express Capability Structure

0x098

Slot Status Register Slot Control Register

PCI Express Capability Structure

0x09C

Root Capabilities Register Root Control Register

PCI Express Capability Structure

0x0A0

Root Status Register

PCI Express Capability Structure

0x0A4

Device Capabilities 2 Register

PCI Express Capability Structure

0x0A8

Device Status 2 Register Device Control 2 Register

PCI Express Capability Structure

0x0AC

Link Capabilities 2 Register

PCI Express Capability Structure

0x0B0

Link Status 2 Register Link Control 2 Register

PCI Express Capability Structure

0x0B4:0x0BC

Reserved

PCI Express Capability Structure

0x800

Advanced Error Reporting Enhanced Capability Header

Advanced Error Reporting Enhanced Capability Header

0x804

Uncorrectable Error Status Register

Uncorrectable Error Status Register

0x808

Uncorrectable Error Mask Register

Uncorrectable Error Mask Register

0x80C

Uncorrectable Error Severity Register

Uncorrectable Error Severity Register

0x810

Correctable Error Status Register

Correctable Error Status Register

0x814

Correctable Error Mask Register

Correctable Error Mask Register

0x818

Advanced Error Capabilities and Control Register

Advanced Error Capabilities and Control Register

0x81C

Header Log Register

Header Log Register

0x82C

Root Error Command

Root Error Command Register

0x830

Root Error Status

Root Error Status Register

0x834

Error Source Identification Register Correctable Error Source ID Register

Error Source Identification Register

Related Information
Level Two Title