Arria V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683773
Date 5/21/2017
Document Table of Contents Configuration Space Register Access Timing

The tl_cfg_add and tl_cfg_ctl signals have multi-cycle paths. They update every eight coreclkout_hip cycles.

Figure 15. Sample tl_cfg_ctl in the Middle of Eight-Cycle Window

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