Visible to Intel only — GUID: lbl1415313393851
Ixiasoft
1. Datasheet
2. Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Design Implementation
9. Additional Features
10. Transceiver PHY IP Reconfiguration
11. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions
5.8. Programming Model for Avalon-MM Root Port
5.9. Uncorrectable Internal Error Mask Register
5.10. Uncorrectable Internal Error Status Register
5.11. Correctable Internal Error Mask Register
5.12. Correctable Internal Error Status Register
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers
5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers
5.7.1.3. PCI Express Mailbox Registers
5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table
5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints
5.7.1.6. Avalon-MM Mailbox Registers
5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
A.4.1. Avalon‑MM Bridge TLPs
A.4.2. Avalon-MM-to-PCI Express Write Requests
A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests
A.4.4. PCI Express-to-Avalon-MM Read Completions
A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests
A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests
A.4.7. Avalon-MM-to-PCI Express Read Completions
A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
A.4.9. Minimizing BAR Sizes and the PCIe Address Space
A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
Visible to Intel only — GUID: lbl1415313393851
Ixiasoft
2.3. Running a Gate-Level Simulation
The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create your own gate-level simulations. Contact your Intel Sales Representative for instructions and an example that illustrates how to create a gate-level simulation from the RTL testbench.