Arria® V Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* Solutions: User Guide

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ID 683773
Date 10/25/2024
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Reset and Clocks 7. Interrupts for Endpoints 8. Error Handling A. PCI Express Protocol Stack 9. Design Implementation 10. Additional Features 11. Transceiver PHY IP Reconfiguration 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. IP Core Verification 1.8. Performance and Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express x
2.1. Running Platform Designer 2.2. Generating the Example Design 2.3. Running a Gate-Level Simulation 2.4. Simulating the Single DWord Design 2.5. Understanding Channel Placement Guidelines 2.6. Generating Synthesis Files 2.7. Compiling the Design in the Quartus® Prime Software 2.8. Programming a Device
3. Parameter Settings x
3.1. Avalon-MM System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. Device Capabilities 3.5. Error Reporting 3.6. Link Capabilities 3.7. MSI and MSI-X Capabilities 3.8. Power Management 3.9. Avalon Memory‑Mapped System Settings
4. Interfaces and Signal Descriptions x
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.6. Physical Layer Interface Signals
4.1. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.1.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.1.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals
4.6. Physical Layer Interface Signals x
4.6.1. Transceiver Reconfiguration 4.6.2. Hard IP Status Extension 4.6.3. Serial Interface Signals 4.6.4. PIPE Interface Signals 4.6.5. Test Signals
4.6.2. Hard IP Status Extension x
4.6.2.1. Configuration Space Register Access 4.6.2.2. Configuration Space Register Access Timing
4.6.3. Serial Interface Signals x
4.6.3.1. Physical Layout of Hard IP in Arria V Devices 4.6.3.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Reset and Clocks x
6.1. Reset Sequence for Hard IP for PCI Express IP Core and Application Layer 6.2. Clocks
6.2. Clocks x
6.2.1. Clock Domains 6.2.2. Clock Summary
6.2.1. Clock Domains x
6.2.1.1. pclk 6.2.1.2. coreclkout_hip 6.2.1.3. pld_clk
7. Interrupts for Endpoints x
7.1. Enabling MSI or Legacy Interrupts 7.2. Generation of Avalon-MM Interrupts 7.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
8. Error Handling x
8.1. Physical Layer Errors 8.2. Data Link Layer Errors 8.3. Transaction Layer Errors 8.4. Error Reporting and Data Poisoning 8.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments 9.3. Recommended Reset Sequence to Avoid Link Training Issues
10. Additional Features x
10.1. Configuration over Protocol (CvP) 10.2. Autonomous Mode 10.3. ECRC
10.2. Autonomous Mode x
10.2.1. Enabling Autonomous Mode 10.2.2. Enabling CvP Initialization
10.3. ECRC x
10.3.1. ECRC on the RX Path 10.3.2. ECRC on the TX Path
11. Transceiver PHY IP Reconfiguration x
11.1. Connecting the Transceiver Reconfiguration Controller IP Core 11.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
D. Document Revision History x
D.1. Arria® V and Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Reset and Clocks
7. Interrupts for Endpoints
8. Error Handling
A. PCI Express Protocol Stack
9. Design Implementation
10. Additional Features
11. Transceiver PHY IP Reconfiguration
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

4.6.2.1. Configuration Space Register Access

The tl_cfg_ctl signal is a multiplexed bus that contains the contents of Configuration Space registers as shown in the figure below. Information stored in the Configuration Space is accessed in round robin order where tl_cfg_add indicates which register is being accessed. The following table shows the layout of configuration information that is multiplexed on tl_cfg_ctl.

Figure 13. Multiplexed Configuration Register Information Available on tl_cfg_ctl Fields in blue are available only for Root Ports.
Table 29.  Configuration Space Register Descriptions

Register

Width

Direction

Description

cfg_dev_ctrl_func<n>

16

Output

cfg_dev_ctrl_func<n>[15:0] is Device Control register for the PCI Express capability structure.
cfg_dev_ctrl2

16

Output

cfg_dev2ctrl[15:0] is Device Control 2 for the PCI Express capability structure.

cfg_slot_ctrl

16

Output

cfg_slot_ctrl[15:0] is the Slot Status of the PCI Express capability structure. This register is only available in Root Port mode.

cfg_link_ctrl

16

Output

cfg_link_ctrl[15:0]is the primary Link Control of the PCI Express capability structure.

For Gen2 operation, you must write a 1’b1 to the Retrain Link bit (Bit[5] of the cfg_link_ctrl) of the Root Port to initiate retraining to a higher data rate after the initial link training to Gen1 L0 state. Retraining directs the LTSSM to the Recovery state. Retraining to a higher data rate is not automatic for the Arria V Hard IP for PCI Express IP Core even if both devices on the link are capable of a higher data rate.

cfg_link_ctrl2

16

Output

cfg_link_ctrl2[31:16] is the secondary Link Control register of the PCI Express capability structure for Gen2 operation.

When tl_cfg_addr=4'b0010, tl_cfg_ctl returns the primary and secondary Link Control registers, { {cfg_link_ctrl[15:0], cfg_link_ctrl2[15:0]}. The primary Link Status register contents are available on tl_cfg_sts[46:31].

For Gen1 variants, the link bandwidth notification bit is always set to 0. For Gen2 variants, this bit is set to 1.

cfg_prm_cmd_func<n>

16

Output

Base/Primary Command register for the PCI Configuration Space.

cfg_root_ctrl

8

Output

Root control and status register of the PCI Express capability. This register is only available in Root Port mode.

cfg_sec_ctrl

16

Output

Secondary bus Control and Status register of the PCI Express capability. This register is available only in Root Port mode.

cfg_secbus

8

Output

Secondary bus number. This register is available only in Root Port mode.

cfg_subbus

8

Output

Subordinate bus number. This register is available only in Root Port mode.

cfg_msi_addr

64

Output

cfg_msi_add[63:32] is the message signaled interrupt (MSI) upper message address. cfg_msi_add[31:0] is the MSI message address.

cfg_io_bas

20

Output

The upper 20 bits of the I/O limit registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_io_lim

20

Output

The upper 20 bits of the IO limit registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_np_bas

12

Output

The upper 12 bits of the memory base register of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_np_lim

12

Output

The upper 12 bits of the memory limit register of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_pr_bas

44

Output

The upper 44 bits of the prefetchable base registers of the Type1 Configuration Space. This register is only available in Root Port mode.

cfg_pr_lim

44

Output

The upper 44 bits of the prefetchable limit registers of the Type1 Configuration Space. Available in Root Port mode.

cfg_pmcsr

32

Output

cfg_pmcsr[31:16] is Power Management Control and cfg_pmcsr[15:0]is the Power Management Status register.

cfg_msixcsr

16

Output

MSI-X message control.

cfg_msicsr

16

Output

MSI message control. Refer to the following table for the fields of this register.

cfg_tcvcmap

24

Output

Configuration traffic class (TC)/virtual channel (VC) mapping. The Application Layer uses this signal to generate a TLP mapped to the appropriate channel based on the traffic class of the packet.

  • cfg_tcvcmap[2:0]: Mapping for TC0 (always 0).
  • cfg_tcvcmap[5:3]: Mapping for TC1.
  • cfg_tcvcmap[8:6]: Mapping for TC2.
  • cfg_tcvcmap[11:9]: Mapping for TC3.
  • cfg_tcvcmap[14:12]: Mapping for TC4.
  • cfg_tcvcmap[17:15]: Mapping for TC5.
  • cfg_tcvcmap[20:18]: Mapping for TC6.
  • cfg_tcvcmap[23:21]: Mapping for TC7.
cfg_msi_data

16

Output

cfg_msi_data[15:0] is message data for MSI.

cfg_busdev

13

Output

Bus/Device Number captured by or programmed in the Hard IP.

Figure 14. Configuration MSI Control Status Register
Table 30.   Configuration MSI Control Status Register Field Descriptions

Bit(s)

Field

Description

[15:9]

Reserved

N/A

[8]

mask capability

Per-vector masking capable. This bit is hardwired to 0 because the function does not support the optional MSI per-vector masking using the Mask_Bits and Pending_Bits registers defined in the PCI Local Bus Specification. Per-vector masking can be implemented using Application Layer registers.

[7]

64-bit address capability

64-bit address capable.

  • 1: function capable of sending a 64-bit message address
  • 0: function not capable of sending a 64-bit message address

[6:4]

multiple message enable

This field indicates permitted values for MSI signals. For example, if “100” is written to this field 16 MSI signals are allocated.

  • 3’b000: 1 MSI allocated
  • 3’b001: 2 MSI allocated
  • 3’b010: 4 MSI allocated
  • 3’b011: 8 MSI allocated
  • 3’b100: 16 MSI allocated
  • 3’b101: 32 MSI allocated
  • 3’b110: Reserved
  • 3’b111: Reserved

[3:1]

multiple message capable

This field is read by system software to determine the number of requested MSI messages.

  • 3’b000: 1 MSI requested
  • 3’b001: 2 MSI requested
  • 3’b010: 4 MSI requested
  • 3’b011: 8 MSI requested
  • 3’b100: 16 MSI requested
  • 3’b101: 32 MSI requested
  • 3’b110: Reserved

[0]

MSI Enable

If set to 0, this component is not permitted to use MSI.

In designs that support multiple functions, host software should not use the MSI Enable bit to mask a function’s MSI’s. Doing so, may leave an MSI request from one function in the pending state, blocking the MSI requests of other functions.

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