1. Using ADI AD9217 with Intel Stratix 10 Devices
AD9217 features a high speed parallel output interface to support its maximum bandwidth capability. It includes digital data path that can be configured for direct real or down converted to complex intelligence quotient (IQ) data. The interface includes 12 data lines, single data clock operating at one-half of ADC sample rate, and a parity bit.
- Data outputs are scrambled to maintain direct current (DC) balance on each data lane. During calibration, the scrambler should remain off.
- A parity bit is generated for each 12-bit sample to detect single bit errors that result from channel-to-channel misalignment. The parity bit is passed along simultaneously with the data sample and it is determined prior to being scrambled.
- The data clock operates at one-half the data rate. Data and the parity bit operate up to 10 Gbps while the clock operates up to 5 GHz.
AD9217 has a low latency chip-to-chip (C2C) output data formats.