AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

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ID 683700
Date 8/17/2020
Public
Document Table of Contents
Document Table of Contents x
1. Using ADI AD9217 with Intel Stratix 10 Devices
1. Using ADI AD9217 with Intel Stratix 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3. Design Description x
1.3.1. Overall Design Flow 1.3.2. Low-Latency C2C Interface
1.3.2. Low-Latency C2C Interface x
1.3.2.1. Lane Mapping in C2C 1.3.2.2. C2C Design Flow 1.3.2.3. Calibration Operation Sequence 1.3.2.4. Calibration Operation Sequence Descriptions
1.5. Parameterization x
1.5.1. Design Parameters 1.5.2. Derived Parameters 1.5.3. Clocks
1.7. Simulation x
1.7.1. Procedure
1.8. Latency Measurement for 10G Design x
1.8.1. Latency Calculations
1.11. Appendix: 5G Design Example x
1.11.1. Hardware Setup 1.11.2. Parameterization 1.11.3. Directory Structure 1.11.4. Simulation 1.11.5. Hardware Testing 1.11.6. Latency Measurement for 5G Design
1.11.2. Parameterization x
1.11.2.1. Design Parameters 1.11.2.2. Derived Parameters 1.11.2.3. Clocks
1.11.4. Simulation x
1.11.4.1. Procedure
1.11.5. Hardware Testing x
1.11.5.1. Procedure
1.11.6. Latency Measurement for 5G Design x
1.11.6.1. Latency Calculations
1. Using ADI AD9217 with Intel Stratix 10 Devices

1.9. Register Map

Table 2.  FPGA Register Map
Address Register Name R/W Bit Field Name Bits Description
0001 C2C_SCRAMBLE_EN R/W c2c_scramble_en [0] Scrambler enable signal.
0010 C2C_OUTPUT_EN R/W c2c_output_en [0] C2C output enable signal as the C2C Valid.
0011 C2C_CHAN_ALIGN_BG_PATT R/W c2c_chan_align_bg_patt [15:0] 16-bit channel alignment BG pattern register.
0100 C2C_CHAN_ALIGN_PATT R/W c2c_chan_align_patt [15:0] 16-bit channel alignment pattern register.
0101 C2C_BREAK_PATT R/W c2c_break_patt [15:0] 16-bit Break Pattern register.
0110 C2C_PARITY_MODE R/W c2c_parity_mod [0] Parity Mode select (0/1).
0111 DATA_PATT_SM_START R/W DATA_PATT_SM_START [0] Data capture start signal to initiate the calibration sequence.
1000 PHY_STATUS R Phy Status [31:0] Transceiver PHY status.
1001 LANE POLARITY R/W Lane polarity [0] To take the Transceiver Lane polarity in FPGA.
1010 C2C_STATUS R C2c status [31:0] C2C status.
1011 BIT REVERSE R Bit reversal [0] To reverse the PHY output.
Level Two Title