AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

ID 683700
Date 8/17/2020
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1.9. Register Map

Table 2.  FPGA Register Map
Address Register Name R/W Bit Field Name Bits Description
0001 C2C_SCRAMBLE_EN R/W c2c_scramble_en [0] Scrambler enable signal.
0010 C2C_OUTPUT_EN R/W c2c_output_en [0] C2C output enable signal as the C2C Valid.
0011 C2C_CHAN_ALIGN_BG_PATT R/W c2c_chan_align_bg_patt [15:0] 16-bit channel alignment BG pattern register.
0100 C2C_CHAN_ALIGN_PATT R/W c2c_chan_align_patt [15:0] 16-bit channel alignment pattern register.
0101 C2C_BREAK_PATT R/W c2c_break_patt [15:0] 16-bit Break Pattern register.
0110 C2C_PARITY_MODE R/W c2c_parity_mod [0] Parity Mode select (0/1).
0111 DATA_PATT_SM_START R/W DATA_PATT_SM_START [0] Data capture start signal to initiate the calibration sequence.
1000 PHY_STATUS R Phy Status [31:0] Transceiver PHY status.
1001 LANE POLARITY R/W Lane polarity [0] To take the Transceiver Lane polarity in FPGA.
1010 C2C_STATUS R C2c status [31:0] C2C status.
1011 BIT REVERSE R Bit reversal [0] To reverse the PHY output.