AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

ID 683700
Date 8/17/2020
Document Table of Contents Calibration Operation Sequence

Table 1.  Calibration Sequence
Step Action Device Details
1 Data capture start asserted FPGA FPGA initiates system startup procedure.
2 FPGA sets DUT scrambling off & sets pattern to clock/data alignment pattern (default is 0xAAAA) FPGA FPGA initiates data and clock alignment.
AD9217 0x4B1 = 0; scrambler off.

0x4A0[3:0] = 1; Select pattern 1 (Reg 0x481 – 0x482).

FPGA transceivers configured FPGA Write appropriate SPI bits.
FPGA transceivers clock data recovery locks FPGA Read appropriate SPI bits to verify bit alignment.
3 FPGA sets DUT pattern to channel word alignment pattern (default is 0xFF00) FPGA FPGA initiates word alignment.
AD9217 0x4A0[3:0] = 2; Select pattern 2 (Reg 0x483 – 0x484).
FPGA transceiver comma detect used to align to word alignment pattern FPGA Read appropriate SPI bits to verify word alignment.
4 FPGA sets DUT pattern to channel alignment pattern (default is 0xB496) FPGA FPGA initiates channel alignment.
AD9217 0x4A0[3:0] = 3; Select pattern 2 (Reg 0x485 – 0x486).
FPGA RTL de-skew channels FPGA Read appropriate SPI bits to verify channel alignment.
5 FPGA sets DUT pattern to ADC data FPGA Set mux for ADC data transmission.
AD9217 0x4A0[3:0] = 0; Selects ADC Data.
DUT sends break word then ADC Data AD9217 Automatically sends break word (0x3333) once then ADC data; 0x4A0[3:0] = 0.
FPGA optionally sets DUT scrambling on after break word seen FPGA Sets scrambling on (recommended).
AD9217 0x4B1[0] = 1; Scrambler on.
6 FPGA starts capturing ADC data FPGA FPGA monitors parity bit.