AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

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ID 683700
Date 8/17/2020
Public
Document Table of Contents
Document Table of Contents x
1. Using ADI AD9217 with Intel Stratix 10 Devices
1. Using ADI AD9217 with Intel Stratix 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3. Design Description x
1.3.1. Overall Design Flow 1.3.2. Low-Latency C2C Interface
1.3.2. Low-Latency C2C Interface x
1.3.2.1. Lane Mapping in C2C 1.3.2.2. C2C Design Flow 1.3.2.3. Calibration Operation Sequence 1.3.2.4. Calibration Operation Sequence Descriptions
1.5. Parameterization x
1.5.1. Design Parameters 1.5.2. Derived Parameters 1.5.3. Clocks
1.7. Simulation x
1.7.1. Procedure
1.8. Latency Measurement for 10G Design x
1.8.1. Latency Calculations
1.11. Appendix: 5G Design Example x
1.11.1. Hardware Setup 1.11.2. Parameterization 1.11.3. Directory Structure 1.11.4. Simulation 1.11.5. Hardware Testing 1.11.6. Latency Measurement for 5G Design
1.11.2. Parameterization x
1.11.2.1. Design Parameters 1.11.2.2. Derived Parameters 1.11.2.3. Clocks
1.11.4. Simulation x
1.11.4.1. Procedure
1.11.5. Hardware Testing x
1.11.5.1. Procedure
1.11.6. Latency Measurement for 5G Design x
1.11.6.1. Latency Calculations
1. Using ADI AD9217 with Intel Stratix 10 Devices

1.3.2.3. Calibration Operation Sequence

Table 1.  Calibration Sequence
Step Action Device Details
1 Data capture start asserted FPGA FPGA initiates system startup procedure.
2 FPGA sets DUT scrambling off & sets pattern to clock/data alignment pattern (default is 0xAAAA) FPGA FPGA initiates data and clock alignment.
AD9217 0x4B1 = 0; scrambler off.

0x4A0[3:0] = 1; Select pattern 1 (Reg 0x481 – 0x482).
FPGA transceivers configured FPGA Write appropriate SPI bits.
FPGA transceivers clock data recovery locks FPGA Read appropriate SPI bits to verify bit alignment.
3 FPGA sets DUT pattern to channel word alignment pattern (default is 0xFF00) FPGA FPGA initiates word alignment.
AD9217 0x4A0[3:0] = 2; Select pattern 2 (Reg 0x483 – 0x484).
FPGA transceiver comma detect used to align to word alignment pattern FPGA Read appropriate SPI bits to verify word alignment.
4 FPGA sets DUT pattern to channel alignment pattern (default is 0xB496) FPGA FPGA initiates channel alignment.
AD9217 0x4A0[3:0] = 3; Select pattern 2 (Reg 0x485 – 0x486).
FPGA RTL de-skew channels FPGA Read appropriate SPI bits to verify channel alignment.
5 FPGA sets DUT pattern to ADC data FPGA Set mux for ADC data transmission.
AD9217 0x4A0[3:0] = 0; Selects ADC Data.
DUT sends break word then ADC Data AD9217 Automatically sends break word (0x3333) once then ADC data; 0x4A0[3:0] = 0.
FPGA optionally sets DUT scrambling on after break word seen FPGA Sets scrambling on (recommended).
AD9217 0x4B1[0] = 1; Scrambler on.
6 FPGA starts capturing ADC data FPGA FPGA monitors parity bit.
Level Two Title