AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

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ID 683700
Date 8/17/2020
Public
Document Table of Contents
Document Table of Contents x
1. Using ADI AD9217 with Intel Stratix 10 Devices
1. Using ADI AD9217 with Intel Stratix 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3. Design Description x
1.3.1. Overall Design Flow 1.3.2. Low-Latency C2C Interface
1.3.2. Low-Latency C2C Interface x
1.3.2.1. Lane Mapping in C2C 1.3.2.2. C2C Design Flow 1.3.2.3. Calibration Operation Sequence 1.3.2.4. Calibration Operation Sequence Descriptions
1.5. Parameterization x
1.5.1. Design Parameters 1.5.2. Derived Parameters 1.5.3. Clocks
1.7. Simulation x
1.7.1. Procedure
1.8. Latency Measurement for 10G Design x
1.8.1. Latency Calculations
1.11. Appendix: 5G Design Example x
1.11.1. Hardware Setup 1.11.2. Parameterization 1.11.3. Directory Structure 1.11.4. Simulation 1.11.5. Hardware Testing 1.11.6. Latency Measurement for 5G Design
1.11.2. Parameterization x
1.11.2.1. Design Parameters 1.11.2.2. Derived Parameters 1.11.2.3. Clocks
1.11.4. Simulation x
1.11.4.1. Procedure
1.11.5. Hardware Testing x
1.11.5.1. Procedure
1.11.6. Latency Measurement for 5G Design x
1.11.6.1. Latency Calculations
1. Using ADI AD9217 with Intel Stratix 10 Devices

1.7.1. Procedure

To run the functional simulation using VCS simulation tool, follow these steps:

  1. In a Terminal window, open the simulation_test_design file, which is present in the design folder.
  2. Change the working directory to simulation_test_design/ll_nphy_tb.
  3. In the command line, type sh run_vcs.sh to invoke the VCS Discovery Visual Environment (DVE).
  4. In the VCS DVE, select File > Load Session from the main menu and select simulation_test_design/load_wave.tcl.
  5. Click Load to load the session.
  6. Run the simulation for 0.5 ms.
  7. When the simulation is completed, observe the output displayed. The following diagrams show the simulation waveforms of the native PHY status output, data pattern generation and C2C states, and latency measurements for 10G design.
Figure 10. Native PHY Status Output
Figure 11. Data Pattern Generation and C2C States
Figure 12. Data at C2C OutputThis simulation waveform has the data at C2C output. Incremental data is provided in each lane and it is observed at C2C output.
Figure 13. Latency Measurement from PHY Transmitter to C2C OutputThis simulation waveform shows the latency measured from the data injected at the PHY transmitter to C2C output. The data 0x001 is a reference for latency measurement, which is highlighted below.
Figure 14. Latency Measurement for 10G Design—107.864 nsThis simulation waveform shows the measured latency for 10G design after adding pipieline registers to close timing.
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