AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

ID 683700
Date 8/17/2020
Document Table of Contents
Give Feedback Lane Mapping in C2C

In the native PHY Transceiver, there are 16 lanes. 16 lanes transceiver is mapped to the C2C interface with 12 data lanes, 1 parity, and a clock.

  • The lane 0 and lane 15 from the transceiver were discarded.
  • The lanes 1 to 6 and lanes 9 to 14 are mapped to the 12 C2C data lanes.
  • Lane 7 and lane 8 of the native PHY Transceiver is mapped to the parity and clock of the C2C interface.
Figure 5. Lane Mapping