1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
126.96.36.199. Calibration Operation Sequence Descriptions
- Data capture start is given by the FPGA to initiate the calibration operation sequence.
- During bit/clock alignment phase, the FPGA sets the alignment pattern and disables the scrambler. The same is done in ADC (AD9217) by configuring the registers 0x4B1 and 0x4A0 through SPI. Once the bit alignment is done in the FPGA, the word alignment phase starts.
- During the word alignment phase, the FPGA sets the alignment pattern. In ADC (AD9217), configure the register 0x4A0 with appropriate bits to select word alignment pattern. Once the word alignment is done, the channel alignment starts in the FPGA.
- During the channel alignment phase, the FPGA sets the alignment pattern. In ADC (AD9217), configure the register 0x4A0 with appropriate bits to select the channel alignment pattern. During this phase, the lane de-skew is taken care in the C2C module.
Figure 6. Channel Alignment in C2C
- In Figure 6, Lane_0 and Lane_2 are aligned and its channel align count is 0. And in Lane_1 and Lane_n, there is a 32-bit delay in data. Therefore, the channel align count is 2.
- Based on the channel align count, the channels are aligned properly.
- After the lane/channel alignment is done and when the break pattern is detected, the scrambler is enabled in both FPGA and AD9217 and the ADC starts the data transmission.
- The FPGA starts capturing the ADC data and monitors the parity bit.
Did you find the information on this page useful?