AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

ID 683700
Date 8/17/2020
Public
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1.11.6.1. Latency Calculations

Speed FPGA Clocking (MHz) Latency on User Interface (C2C) (ns) Latency on Transceiver Parallel Data (Native PHY FPGA Interface) (ns)
5GT/s (5GSps) 156.25 179.2 140.8

For designs with the lane rate of 5 Gbps:

  • PHY receiver clock = (Lane rate/32 = 5000e6/32) = 156.25 MHz.
  • Clock period of 156.25 MHz = 6.4 ns.
  • Number of clock cycles between pulse injected at the ADC input to pulse observed at C2C output – 28 clock cycles of PHY receiver clock.
  • Latency measured at the C2C output = 6.4 ns * 28 = 179.2 ns.
  • Since the C2C design in the FPGA has a constant delay of 6 clock cycles, this can be excluded from overall latency so that the latency can get up to receive transceiver.
  • Latency measured at the transceiver output = 6.4 ns * (28-6) = 140.8 ns.