1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
18.104.22.168. Latency Calculations
|Speed||FPGA Clocking (MHz)||Latency on User Interface (C2C) (ns)||Latency on Transceiver Parallel Data (Native PHY FPGA Interface) (ns)|
For designs with the lane rate of 5 Gbps:
- PHY receiver clock = (Lane rate/32 = 5000e6/32) = 156.25 MHz.
- Clock period of 156.25 MHz = 6.4 ns.
- Number of clock cycles between pulse injected at the ADC input to pulse observed at C2C output – 28 clock cycles of PHY receiver clock.
- Latency measured at the C2C output = 6.4 ns * 28 = 179.2 ns.
- Since the C2C design in the FPGA has a constant delay of 6 clock cycles, this can be excluded from overall latency so that the latency can get up to receive transceiver.
- Latency measured at the transceiver output = 6.4 ns * (28-6) = 140.8 ns.