ID 683700
Date 8/17/2020
Public
Give Feedback

## 1.8.1. Latency Calculations

Speed FPGA Clocking (MHz) Latency on User Interface (C2C) (ns) Latency on Transceiver Parallel Data (Native PHY FPGA Interface) (ns)
5GT/s (5GSps) 156.25 179.2 140.8
10GT/s (10GSps) 1 312.5 99.2 80

For designs with the lane rate of 5 Gbps:

• PHY receiver clock = (Lane rate/32 = 5000e6/32) = 156.25 MHz.
• Clock period of 156.25 MHz = 6.4 ns.
• Number of clock cycles between pulse injected at the ADC input to pulse observed at C2C output – 28 clock cycles of PHY receiver clock.
• Latency measured at the C2C output = 6.4 ns * 28 = 179.2 ns.
• Since the C2C design in the FPGA has a constant delay of 6 clock cycles, this can be excluded from overall latency so that the latency can get up to receive transceiver.
• Latency measured at the transceiver output = 6.4 ns * (28-6) = 140.8 ns.

Considering the above calculation, the latency for 10G lane rate is derived and shown below:

• PHY receiver clock = (lane rate/32 = 10000e6/32) = 312.5 MHz.
• Clock period of 312.5 MHz = 3.2 ns.
• Number of clock cycles between pulse injected at ADC input to pulse observed at C2C output – 28 clock cycles of PHY receiver clock.
• Latency measured at the C2C output = 3.2 ns * 28 = 89.6 ns.
• C2C latency in clock cycles = 6 clock cycles.
• Latency measured at the transceiver output = 3.2 ns * (28-6) = 70.4 ns.
After considering the pipeline delays in 10G designs, the latency is further increased to 3 clock cycles:
Note: Pipeline stages is added to close timing in 10G designs.
• Total latency measured = 3.2 ns * 31 = 99.2 ns.
• C2C latency in clock cycles = 6 clock cycles.
• Latency measured at transceiver output = 3.2 ns * (31-6) = 80 ns.
1 The latency for 10G lane rate is derived by considering the 5G design calculations and added pipelines to close timing in 10G designs (3 clock cycles).