AN 882: Using ADI AD9217 with Intel® Stratix® 10 Devices

ID 683700
Date 8/17/2020
Public
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1.3.2. Low-Latency C2C Interface

The FPGA program supports the low-latency chip-to-chip (C2C) interface mode.
  • In C2C mode, the FPGA controls the C2C pattern select and scramble fields of the ADC to implement the C2C alignment sequence.
  • The FPGA de-asserts scrambling during alignment and enables scrambling after alignment is complete.
  • FPGA supports inverted or non-inverted parity.
  • Before running C2C mode, the ADC and FPGA C2C alignment pattern values must be set the same.