1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Design Description 1.4. Functional Description 1.5. Parameterization 1.6. Directory Structure 1.7. Simulation 1.8. Latency Measurement for 10G Design 1.9. Register Map 1.10. Document Revision History for AN 882: Using ADI AD9217 with Intel Stratix 10 Devices 1.11. Appendix: 5G Design Example
1.3.2. Low-Latency C2C Interface
The FPGA program supports the low-latency chip-to-chip (C2C) interface mode.
- In C2C mode, the FPGA controls the C2C pattern select and scramble fields of the ADC to implement the C2C alignment sequence.
- The FPGA de-asserts scrambling during alignment and enables scrambling after alignment is complete.
- FPGA supports inverted or non-inverted parity.
- Before running C2C mode, the ADC and FPGA C2C alignment pattern values must be set the same.