AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
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Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA

The following types of Cyclone® V and Arria® V HPS peripherals are capable of routing to the FPGA fabric:

  • Ethernet Media Access Controller (EMAC)
  • Quad Serial Peripheral Interface (QSPI)
  • Secure Digital/Multimedia Card (SD/MMC)
  • Serial Peripheral Interface (SPI)
  • Universal Asynchronous Receiver/Transmitter (UART)
  • Inter-Integrated Circuit (I2C)
  • Controller Area Network (CAN)1

In many cases, routing the HPS IP signals to the FPGA external interface allows more signals to be exposed.

Table 1.  Peripherals that Support Signal Routing from the HPS Domain to FPGA DomainThe following table lists the interface type that is available depending on whether the IP interface is pinned out in the HPS domain or the FPGA domain.

Peripherals

Interface Description
 

HPS Domain

FPGA Domain

EMAC

RGMII Interface

GMII Interface

QSPI

Standard QSPI interface with four slave select signals

Standard QSPI interface with four slave select signals achieved by connecting exported signals to bidirectional buffers

SD/MMC Standard SD/MMC interface with up to 8-bit data bus Standard SD/MMC interface, including:
  • Up to 8-bit data bus
  • Card detect interface
  • Card interrupt
  • Voltage switching
  • Power enable
  • Reset 2

SPI Master

MOSI/MISO SPI interface configurable to single or dual slaves

MOSI/MISO SPI interface with output enables that support up to four slaves; interface achieved by connecting exported signals to bidirectional buffers

SPI Slave

MOSI/MISO SPI interface configurable to single or dual slaves

MOSI/MISO SPI interface with output enables that support up to four slaves; interface achieved by connecting exported signals to bidirectional buffers

UART

Standard UART interface with flow control signals

Standard UART interface with flow control signals, including DTR and DSR; status and two user-defined output signals are also available

I2C

Standard I2C interface

Standard I2C interface achieved by connecting exported signals to a bidirectional buffer

CAN3

Standard CAN interface

Standard CAN interface

Refer to the following chapters of the Cyclone® V Hard Processor System Technical Reference Manual for descriptions of each peripheral signal interface:

Related Information
1 The CAN interface is only available in the Cyclone® V SoC device family.
2 The SD/MMC controller does not directly support reset, voltage switching, card interrupts, power enable or write protect functions. However, you can connect these signals to general-purpose I/Os (GPIOs).
3 The CAN interface is only available in the Cyclone® V SoC device family.
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