AN 706: Routing HPS Peripheral Signals to the FPGA External Interface
ID
683659
Date
5/07/2018
Public
1.2.1. Prerequisites
1.2.2. Getting Started
1.2.3. Generating the Initial HDL in Platform Designer (Standard)
1.2.4. Top Level Routing
1.2.5. Timing Constraint Configuration
1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition
1.2.7. Hardware Programming File Compilation and Generation
1.2.8. SD Card Image Updates
1.2.9. Board Setup and Booting Linux from the SD Card
1.2.5. Timing Constraint Configuration
Replace the soc_system_timing.sdc file in your project directory with the soc_system_timing.sdc file provided in the project folder. This new file is customized for the EMAC0 and I2C0 interface being tested on the Cyclone® V SoC development board.