AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

ID 683659
Date 5/07/2018

1.2.5. Timing Constraint Configuration

Replace the soc_system_timing.sdc file in your project directory with the soc_system_timing.sdc file provided in the project folder. This new file is customized for the EMAC0 and I2C0 interface being tested on the Cyclone® V SoC development board.