AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

ID 683659
Date 5/07/2018

1.2.7. Hardware Programming File Compilation and Generation

After the Platform Designer (Standard) system is set up, the top level RTL file updated, the related signal pin location assigned and timing constrained, the design can be compiled and the SOF programming file generated.

In the Intel® Quartus® Prime Standard Edition software navigation bar, select Processing > Start Compilation to generate the SOF programming file.