AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.3.2. I2C Test

The I2C interface can be tested using the following commands: 

>i2cdetect -l
List the detected HPS I2C ports. 
>i2cdetect -r 0
List the I2C slave devices connected to the HPS. "UU" is defined as device busy.
Figure 13.  i2cdetect Command Outputs 
>i2cset -y 0 0x66 0x10 0x55
I2C0 writes the data value 0x55 to the data address 0x10 of slave device at 0x66. The command is written in the order: device address, data address, data value. 
>i2cget -y 0 0x66 0x10
Return data value at address 0x10 of the device slave at address 0x66.
Figure 14.  i2cset and i2cget Commands 
>i2cdump -y 0 0x66
Register data dump from 0x00 to 0xFF. "XX" is defined as a non-valid address.
Figure 15.  i2cdump Command Output
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