AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.2.1.2. Software Requirements

The software required for this design example is:

  • Intel® Quartus® Prime Standard Edition 14.0 and above
  • SoC EDS 14.0 and above
  • Factory default hardware template cv_soc_devkit_ghrd in SoC EDS 14.0

Design example files are provided in the AN 706 design example link and are listed in the table below.

Table 2.   Required Software Files

File Name

Description

ghrd_top.v

Top level RTL file

soc_system_timing.sdc

Timing constraint file

an706_de_pin_assignment.tcl

Pin assignment script file

preloader-mkpimage.bin

Generated preloader binary targeted to this project

u-boot.img

Modified u-boot image for EMAC0

socfpga.dtb

Modified device tree for EMAC0 and I2C0
Level Two Title