AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

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ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition

  1. Copy an706_de_pin_assignment.tcl from the AN 706 design files into your project directory.
  2. In the Intel® Quartus® Prime Standard Edition menu bar, select Tools > Tcl Scripts
  3. In the Tcl Scripts window, choose an706_de_pin_assignment.tcl and select Run.
    Figure 7. Selecting pin_assigment.tcl in the Tcl Scripts Window
    The an706_de_pin_assignment.tcl script automatically assigns EMAC0 and I2C0 signal pins to their related FPGA pin location.
    Table 5.  Pin Assignments for EMAC0 and I2C0

    Signal

    Direction

    Pin Location

    enet1_rx_clk

    Input

    		 PIN_Y24
    enet1_rx_d[0]

    Input

    		 PIN_AB23
    enet1_rx_d[1]

    Input

    		 PIN_AA24
    enet1_rx_d[2]

    Input

    		 PIN_AB25
    enet1_rx_d[3]

    Input

    		 PIN_AE27
    enet1_rx_dv

    Input

    		 PIN_Y23
    enet1_rx_error

    Input

    		 PIN_AE28
    enet1_tx_clk_fb

    Input

    		 PIN_W25
    enet1_tx_d[0]

    Output

    		 PIN_W20
    enet1_tx_d[1]

    Output

    		 PIN_Y21
    enet1_tx_d[2]

    Output

    		 PIN_AA25
    enet1_tx_d[3]

    Output

    		 PIN_AB26
    enet1_tx_en

    Output

    		 PIN_AB22
    enet1_tx_error

    Output

    		 PIN_AG5
    enet_dual_resetn

    Output

    		 PIN_AJ1
    enet_fpga_mdc

    Output

    		 PIN_H12
    enet_fpga_mdio

    Bidirectional

    		 PIN_H13
    fpga_i2c_scl

    Bidirectional

    		 PIN_G7
    fpga_i2c_sda

    Bidirectional

    		 PIN_F6
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