AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

ID 683659
Date 5/07/2018

1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

The Intel Cyclone® V and Arria® V SoC device families integrate an Arm* Cortex* -A9-based hard processor system (HPS) consisting of processor, peripherals, and memory interface with the FPGA fabric using a high-bandwidth interconnect backbone. The Cyclone® V HPS interface provides up to 67 I/O pins to share with multiple peripherals through sets of configurable multiplexers. The Arria® V HPS interface provides up to 71 I/O pins.

This application note describes the steps required to route an HPS peripheral through the FPGA interface using Platform Designer (Standard) and Intel® Quartus® Prime Standard Edition software. A simple design example is included to demonstrate exporting HPS EMAC0 and I2C0 peripheral signals to the FPGA interface using a Cyclone® V SoC Development Kit.