AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

Download PDF
ID 683659
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface x
1.1. Cyclone® V and Arria® V HPS Peripherals That Support Routing to the FPGA 1.2. Design Example: Cyclone® V HPS IP Interface to FPGA 1.3. Sample Application Example 1.4. Reference Documents 1.5. AN 706 Revision History
1.2. Design Example: Cyclone® V HPS IP Interface to FPGA x
1.2.1. Prerequisites 1.2.2. Getting Started 1.2.3. Generating the Initial HDL in Platform Designer (Standard) 1.2.4. Top Level Routing 1.2.5. Timing Constraint Configuration 1.2.6. Adding Pin Assignments in Intel® Quartus® Prime Standard Edition 1.2.7. Hardware Programming File Compilation and Generation 1.2.8. SD Card Image Updates 1.2.9. Board Setup and Booting Linux from the SD Card
1.2.1. Prerequisites x
1.2.1.1. Hardware Requirements 1.2.1.2. Software Requirements
1.2.8. SD Card Image Updates x
1.2.8.1. Preloader Generation 1.2.8.2. U-boot Setup 1.2.8.3. Device Tree Setup
1.3. Sample Application Example x
1.3.1. EMAC Test 1.3.2. I2C Test
1. AN 706: Mapping HPS IP Peripheral Signals to the FPGA Interface

1.2. Design Example: Cyclone® V HPS IP Interface to FPGA

This design example, based on the Golden System Reference Design (GSRD), uses the Cyclone® V SoC development kit resources to demonstrate routing the Cyclone® V HPS EMAC0 and I2C0 peripheral signals to the FPGA interface.

The Cyclone® V HPS component provides up to two EMAC peripherals, which support 10/100/1000 Mbps operation. The Cyclone® V SoC Development board is populated with a Micrel KSZ9021RN RGMII PHY that interfaces to the HPS domain and a Renesas uPD60620A MII Dual Port PHY that interfaces to the FPGA domain. The HPS and FPGA also share a common I2C bus to various on-board I2C slaves.

Figure 1. High-level Routing Layout of Cyclone® V SoC Board Design Example

The following sections provide the necessary information to route the HPS peripherals to the FPGA interface, such as:

  1. Prerequisites
  2. Getting Started
  3. Generating the Initial HDL in Platform Designer (Standard)
  4. Top Level Routing
  5. Timing Constraint Configuration
  6. Adding Pin Assignments in Intel Quartus Prime Standard Edition
  7. Hardware Programming File Compilation and Generation
  8. SD Card Image Updates
  9. Board Setup and Booting Linux from the SD Card
Level Two Title