AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

ID 683659
Date 5/07/2018

1.2. Design Example: Cyclone® V HPS IP Interface to FPGA

This design example, based on the Golden System Reference Design (GSRD), uses the Cyclone® V SoC development kit resources to demonstrate routing the Cyclone® V HPS EMAC0 and I2C0 peripheral signals to the FPGA interface.

The Cyclone® V HPS component provides up to two EMAC peripherals, which support 10/100/1000 Mbps operation. The Cyclone® V SoC Development board is populated with a Micrel KSZ9021RN RGMII PHY that interfaces to the HPS domain and a Renesas uPD60620A MII Dual Port PHY that interfaces to the FPGA domain. The HPS and FPGA also share a common I2C bus to various on-board I2C slaves.

Figure 1. High-level Routing Layout of Cyclone® V SoC Board Design Example

The following sections provide the necessary information to route the HPS peripherals to the FPGA interface, such as: