AN 706: Routing HPS Peripheral Signals to the FPGA External Interface

ID 683659
Date 5/07/2018

1.2.4. Top Level Routing

The top level RTL file defines the pin connections from the Cyclone® V HPS EMAC0 to the Renesas MII PHY on the Cyclone® V SoC development board.
Note: Because MII is a 4-bit data width protocol, connect only the lower 4-bits, emac0_phy_txd_o[3:0] and emac0_phy_rxd_i[3:0], of EMAC0's RX and TX interface from the FPGA.
Figure 6. Routing of the EMAC0 FPGA Interface to the On-board MII PHY

HPS I2C0 is routed through the FPGA interface and acts as a master to various on-board I2C slaves:

  • Two Octal Digital Power Supply Managers with EEPROM
  • LCD
  • RTC
Note: A bi-directional buffer, ALT_IOBUF, must be added in the design to connect the I2C signals to an external open drain IO. The buffer can be included by instantiating ALT_IOBUF in ghrd_top.v.

The following Verilog code shows the ALT_IOBUF instantiation for an I2C interface implemented through the FPGA:

ALT_IOBUF scl_iobuf (.i(1'b0), .oe(scl_o_e), .o(scl_o), .io(fpga_i2c_scl)); //declared bi-directional buffer for scl
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(sda_o_e), .o(sda_o), .io(fpga_i2c_sda)); //declared bi-directional buffer for sda