Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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1.3. Optimization Trade-Offs and Limitations

Design optimization is often a trade-off between performance, resource usage, power utilization, and compilation time. You can apply various settings to achieve the correct balance of these factors for your design goals.
Table 1.  Design Optimization Trade-Off Examples
Trade-off Comments
Resource usage and critical path timing. Certain techniques (such as logic duplication) can improve timing performance at the cost of increased area.
Power requirements can result in area and timing trade-offs. For example, reducing the number of available high-speed tiles, or attempting to shorten high-power nets at the expense of critical path nets.
System cost and time-to-market considerations can affect the choice of device. For example, a device with a higher speed grade or more clock networks can facilitate timing closure at the expense of higher power consumption and system cost.

Finally, constraints that are too stringent can produce a situation with no possible solution for the selected device. If the Fitter cannot resolve a design due to resource limitations, timing constraints, or power constraints, consider rewriting parts of the HDL code.