Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5.8.2. Optimize IOC Register Placement for Timing Logic Option

This option moves registers into I/O elements to meet tSU or tCO assignments, duplicating the register if necessary (as in the case in which a register fans out to multiple output locations). This option is turned on by default and is a global setting.
The Optimize IOC Register Placement for Timing logic option affects only pins that have a tSU or tCO requirement. Using the I/O register is possible only if the register directly feeds a pin or is fed directly by a pin. Therefore, this logic option does not affect registers with any of the following characteristics:
Note: To optimize registers with these characteristics, use other Intel® Quartus® Prime Fitter optimizations.
  • Have combinational logic between the register and the pin
  • Are part of a carry chain
  • Have an overriding location assignment
  • Use the asynchronous load port and the value is not 1 (in device families where the port is available)