Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3. Netlist Optimizations and Physical Synthesis

The Intel® Quartus® Prime software offers netlist optimizations during synthesis, and physical synthesis optimization during fitting, that can improve the performance of your design. Synthesis netlist optimizations operate with the atom netlist of your design, which describes a design in terms of specific primitives. This chapter provides guidelines for applying synthesis and physical synthesis optimization settings.

You can access a range of global synthesis and physical synthesis optimization settings from the Compiler Settings page:

Table 8.  Synthesis Netlist Optimization and Physical Synthesis Options
Options Location/Description
Enable synthesis netlist optimization settings Enable synthesis optimization options (for example, Synthesis Effort) in the Advanced Synthesis Settings dialog box. Click Assignments > Settings > Compiler Settings > Advanced Settings (Synthesis) to access these options.
Enable physical synthesis options Enable physical synthesis options (for example, Advanced Physical Synthesis) in the Advanced Fitter Settings dialog box. Click Assignments > Settings > Compiler Settings > Advanced Settings (Fitter) to access these settings.
Note: Because the node names for primitives in the design can change when you use physical synthesis optimizations, you should evaluate whether your design depends on fixed node names. If you use a verification flow that might require fixed node names, such as the Signal Tap Logic Analyzer, formal verification, or the Logic Lock based optimization flow (for legacy devices), disable physical synthesis options.