Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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1.2.1. Initial I/O Assignment Guidelines

In a FPGA design, I/O standards and drive strengths affect I/O timing. Follow these guidelines when specifying initial I/O assignments:
  • When specifying I/O assignments, make sure that the Intel® Quartus® Prime software is using an accurate I/O timing delay for timing analysis and Fitter optimizations.
  • If the PCB layout does not indicate pin locations, then leave the pin locations unconstrained. This technique allows the Compiler to search for the best layout. Otherwise, make pin assignments to constrain the compilation appropriately.