Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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Document Table of Contents Tips for Analyzing Failing Clock Paths that Cross Clock Domains

When analyzing clock path failures:

  • Check whether these paths cross two clock domains. In paths that cross two clock domains, the From Clock and To Clock in the timing analysis report are different.
    Figure 53. Different Value in From Clock and To Clock Field
  • Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same.
  • Check whether failing paths between these clock domains need to be analyzed synchronously. Set failing paths that are not to be analyzed synchronously as false paths.
  • When you run report_timing on a design, the report shows the launch clock and latch clock for each failing path. Check whether the relationship between the launch clock and latch clock is realistic and what you expect from your knowledge of the design. For example, the path can start at a rising edge and end at a falling edge, which reduces the setup relationship by one half clock cycle.
  • Review the clock skew that appears in the Timing Report. A large skew may indicate a problem in the design, such as a gated clock, or a problem in the physical layout (for example, a clock using local routing instead of dedicated clock routing). When you have made sure the paths are analyzed synchronously and that there is no large skew on the path, and that the constraints are correct, you can analyze the data path. These steps help you fine tune your constraints for paths across clock domains to ensure you get an accurate timing report.
  • Check if the PLL phase shift is reducing the setup requirement. You might adjust this by using PLL parameters and settings.
  • Ignore paths that cross clock domains for logic protected with synchronization logic (for example, FIFOs or double-data synchronization registers), even if the clocks are related.
  • Set false path constraints on all unnecessary paths. Attempting to optimize unnecessary paths can prevent the Fitter from meeting the timing requirements on timing paths that are critical to the design.