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1. Design Optimization Overview 2. Optimizing the Design Netlist 3. Netlist Optimizations and Physical Synthesis 4. Area Optimization 5. Timing Closure and Optimization 6. Analyzing and Optimizing the Design Floorplan 7. Using the ECO Compilation Flow 8. Intel® Quartus® Prime Pro Edition Design Optimization User Guide Archives A. Intel® Quartus® Prime Pro Edition User Guides
2.1. When to Use the Netlist Viewers: Analyzing Design Problems 2.2. Intel® Quartus® Prime Design Flow with the Netlist Viewers 2.3. RTL Viewer Overview 2.4. Technology Map Viewer Overview 2.5. Netlist Viewer User Interface 2.6. Schematic View 2.7. Cross-Probing to a Source Design File and Other Intel® Quartus® Prime Windows 2.8. Cross-Probing to the Netlist Viewers from Other Intel® Quartus® Prime Windows 2.9. Viewing a Timing Path 2.10. Optimizing the Design Netlist Revision History
2.6.1. Display Schematics in Multiple Tabbed View 2.6.2. Schematic Symbols 2.6.3. Select Items in the Schematic View 2.6.4. Shortcut Menu Commands in the Schematic View 2.6.5. Filtering in the Schematic View 2.6.6. View Contents of Nodes in the Schematic View 2.6.7. Moving Nodes in the Schematic View 2.6.8. View LUT Representations in the Technology Map Viewer 2.6.9. Zoom Controls 2.6.10. Navigating with the Bird's Eye View 2.6.11. Partition the Schematic into Pages 2.6.12. Follow Nets Across Schematic Pages
184.108.40.206. Guideline: Optimize Source Code 220.127.116.11. Guideline: Optimize Synthesis for Area, Not Speed 18.104.22.168. Guideline: Restructure Multiplexers 22.214.171.124. Guideline: Perform WYSIWYG Primitive Resynthesis with Balanced or Area Setting 126.96.36.199. Guideline: Use Register Packing 188.8.131.52. Guideline: Remove Fitter Constraints 184.108.40.206. Guideline: Flatten the Hierarchy During Synthesis 220.127.116.11. Guideline: Re-target Memory Blocks 18.104.22.168. Guideline: Use Physical Synthesis Options to Reduce Area 22.214.171.124. Guideline: Retarget or Balance DSP Blocks 126.96.36.199. Guideline: Use a Larger Device
188.8.131.52. Guideline: Set Auto Packed Registers to Sparse or Sparse Auto 184.108.40.206. Guideline: Set Fitter Aggressive Routability Optimizations to Always 220.127.116.11. Guideline: Increase Router Effort Multiplier 18.104.22.168. Guideline: Remove Fitter Constraints 22.214.171.124. Guideline: Optimize Synthesis for Area, Not Speed 126.96.36.199. Guideline: Optimize Source Code 188.8.131.52. Guideline: Use a Larger Device
5.1. Optimize Multi Corner Timing 5.2. Optimize Critical Paths 5.3. Optimize Critical Chains 5.4. Design Evaluation for Timing Closure 5.5. Timing Optimization 5.6. Periphery to Core Register Placement and Routing Optimization 5.7. Scripting Support 5.8. Timing Closure and Optimization Revision History
5.5.1. Correct Design Assistant Rule Violations 5.5.2. Implement Fast Forward Timing Closure Recommendations 5.5.3. View Timing Optimization Advisor 5.5.4. Review Timing Path Details 5.5.5. Try Optional Fitter Settings 5.5.6. Back-Annotate Optimized Assignments 5.5.7. Optimize Settings with Design Space Explorer II 5.5.8. I/O Timing Optimization Techniques 5.5.9. Register-to-Register Timing Optimization Techniques 5.5.10. Metastability Analysis and Optimization Techniques
184.108.40.206. Report Timing 220.127.116.11. Report Logic Depth 18.104.22.168. Report Neighbor Paths 22.214.171.124. Report Register Spread 126.96.36.199. Report Route Net of Interest 188.8.131.52. Report Retiming Restrictions 184.108.40.206. Report Pipelining Information 220.127.116.11. Report CDC Viewer 18.104.22.168. Timing Closure Recommendations 22.214.171.124. Global Network Buffers 126.96.36.199. Resets and Global Networks 188.8.131.52. Suspicious Setup 184.108.40.206. Auto Shift Register Replacement 220.127.116.11. Clocking Architecture
18.104.22.168. I/O Timing Constraints 22.214.171.124. Optimize IOC Register Placement for Timing Logic Option 126.96.36.199. Fast Input, Output, and Output Enable Registers 188.8.131.52. Programmable Delays 184.108.40.206. Use PLLs to Shift Clock Edges 220.127.116.11. Use Fast Regional Clock Networks and Regional Clocks Networks 18.104.22.168. Spine Clock Limitations
22.214.171.124. Optimize Source Code 126.96.36.199. Improving Register-to-Register Timing 188.8.131.52. Physical Synthesis Optimizations 184.108.40.206. Set Power Optimization During Synthesis to Normal Compilation 220.127.116.11. Optimize Synthesis for Speed, Not Area 18.104.22.168. Flatten the Hierarchy During Synthesis 22.214.171.124. Set the Synthesis Effort to High 126.96.36.199. Duplicate Registers for Fan-Out Control 188.8.131.52. Prevent Shift Register Inference 184.108.40.206. Use Other Synthesis Options Available in Your Synthesis Tool 220.127.116.11. Fitter Seed 18.104.22.168. Set Maximum Router Timing Optimization Level 22.214.171.124. Register-to-Register Timing Analysis
6.1. Design Floorplan Analysis in the Chip Planner 6.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner 6.3. Using Logic Lock Regions in the Chip Planner 6.4. Using User-Defined Clock Regions in the Chip Planner 6.5. Scripting Support 6.6. Analyzing and Optimizing the Design Floorplan Revision History
126.96.36.199. Viewing Architecture-Specific Design Information 188.8.131.52. Viewing Available Clock Networks in the Device 184.108.40.206. Viewing Clock Sector Utilization 220.127.116.11. Viewing Routing Congestion 18.104.22.168. Viewing I/O Banks 22.214.171.124. Viewing High-Speed Serial Interfaces (HSSI) 126.96.36.199. Viewing the Source and Destination of Placed Nodes 188.8.131.52. Viewing Fan-In and Fan-Out Connections of Placed Resources 184.108.40.206. Viewing Immediate Fan-In and Fan-Out Connections 220.127.116.11. Viewing Selected Contents
6.3.1. Viewing Connections Between Logic Lock Regions in the Chip Planner 6.3.2. Logic Lock Regions 6.3.3. Attributes of a Logic Lock Region 6.3.4. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition 6.3.5. Creating Logic Lock Regions 6.3.6. Customizing the Shape of Logic Lock Regions 6.3.7. Placing Device Resources into Logic Lock Regions 6.3.8. Hierarchical Regions 6.3.9. Additional Intel® Quartus® Prime Logic Lock Design Features 6.3.10. Logic Lock Regions Window 6.3.11. Snapping to a Region
18.104.22.168. Creating Logic Lock Regions with the Chip Planner 22.214.171.124. Creating Logic Lock Regions with the Project Navigator 126.96.36.199. Creating Logic Lock Regions with the Logic Lock Regions Window 188.8.131.52. Defining Routing Regions 184.108.40.206. Noncontiguous Logic Lock Regions 220.127.116.11. Considerations on Using Auto Sized Regions
7.4.1. ECO Command Quick Reference 7.4.2. make_connection 7.4.3. remove_connection 7.4.4. modify_lutmask 7.4.5. adjust_pll_refclk 7.4.6. modify_io_slew_rate 7.4.7. modify_io_current_strength 7.4.8. modify_io_delay_chain 7.4.9. create_new_node 7.4.10. remove_node 7.4.11. place_node 7.4.12. unplace_node 7.4.13. create_wirelut
6.2. Creating Partitions and Logic Lock Regions with the Design Partition Planner and the Chip Planner
- 6.3.4. Migrating Assignments between Intel® Quartus® Prime Standard Edition and Intel® Quartus® Prime Pro Edition
18.104.22.168.2. Tips for Analyzing Failing Clock Paths that Cross Clock Domains
When analyzing clock path failures:
- Check whether these paths cross two clock domains. In paths that cross two clock domains, the From Clock and To Clock in the timing analysis report are different.
Figure 53. Different Value in From Clock and To Clock Field
- Check if the design contains paths that involve a different clock in the middle of the path, even if the source and destination register clock are the same.
- Check whether failing paths between these clock domains need to be analyzed synchronously. Set failing paths that are not to be analyzed synchronously as false paths.
- When you run report_timing on a design, the report shows the launch clock and latch clock for each failing path. Check whether the relationship between the launch clock and latch clock is realistic and what you expect from your knowledge of the design. For example, the path can start at a rising edge and end at a falling edge, which reduces the setup relationship by one half clock cycle.
- Review the clock skew that appears in the Timing Report. A large skew may indicate a problem in the design, such as a gated clock, or a problem in the physical layout (for example, a clock using local routing instead of dedicated clock routing). When you have made sure the paths are analyzed synchronously and that there is no large skew on the path, and that the constraints are correct, you can analyze the data path. These steps help you fine tune your constraints for paths across clock domains to ensure you get an accurate timing report.
- Check if the PLL phase shift is reducing the setup requirement. You might adjust this by using PLL parameters and settings.
- Ignore paths that cross clock domains for logic protected with synchronization logic (for example, FIFOs or double-data synchronization registers), even if the clocks are related.
- Set false path constraints on all unnecessary paths. Attempting to optimize unnecessary paths can prevent the Fitter from meeting the timing requirements on timing paths that are critical to the design.
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