Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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6.1.3. Viewing Design Elements in the Chip Planner

The Chip Planner allows you to locate and report details on various elements of your design, such as viewing available clock networks, routing congestion, I/O banks, and high-speed serial interfaces in the floorplan.

The following section described how to view various design elements in the Chip Planner.