Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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Document Table of Contents

1.4.1. Design Visualization Tools

The Intel® Quartus® Prime software provides tools that display different graphical representations of your design to help you visualize and optimize placement, connectivity, and routing congestion at various stages of the design cycle.

Table 2.  Design Visualization Tools
Tool Description
RTL Viewer Provides a schematic representation of the design before synthesis and place-and-route.
Technology Map Viewer Provides a schematic representation of the design implementation in the selected device architecture after synthesis and place-and-route. Optionally, you can include timing information.
Chip Planner Allows you to make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion.
Interface Planner Simplifies the planning of accurate constraints for physical implementation. Use Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan.
State Machine Viewer Presents a high-level, graphical view of finite state machines in your design. The viewer displays the states and their related transitions, as well as a state transition table with condition equations for state transitions, and encoding information for each state.
Design Partition Planner Displays design entities, I/O banks, connectivity, design hierarchy, and design partition membership. Design Partition Planner can assist you in visualizing a design's structure for creating effective design partitions.
Design Partition Planner and Chip Planner Allows you to partition and layout the design at a higher level chip view.