Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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Document Table of Contents

6.1. Design Floorplan Analysis in the Chip Planner

The Chip Planner simplifies floorplan analysis by providing visual display of chip resources. With the Chip Planner, you can view post-compilation placement, connections, and routing paths. You can also make assignment changes, such as creating and deleting resource assignments.

The Chip Planner showcases:

  • Logic Lock regions
  • Relative resource usage
  • Detailed routing information
  • Fan-in and fan-out connections between nodes
  • Timing paths between registers
  • Delay estimates for paths
  • Routing congestion information