Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 10/04/2021

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6. Analyzing and Optimizing the Design Floorplan

As FPGA designs grow larger in density, the ability to analyze the design for performance, routing congestion, and logic placement is critical to meet the design requirements. This chapter discusses how the Chip Planner and Logic Lock regions help you improve your design's floorplan.

Design floorplan analysis helps to close timing, and ensures optimal performance in highly complex designs. With analysis capability, the Intel® Quartus® Prime Chip Planner helps you close timing quickly on your designs. You can use the Chip Planner together with Logic Lock regions to compile your designs hierarchically and assist with floorplanning. Additionally, use partitions to preserve placement and routing results from individual compilation runs.

You can perform design analysis, as well as create and optimize the design floorplan with the Chip Planner. To make I/O assignments, use the Pin Planner.

Note: As a best practice, define resource placement with iterative design flows. Use techniques like the Early Place Flow to guide your floorplanning decisions before setting hard placement constraints.

For information about the Early Place Flow, refer to the Intel® Quartus® Prime Pro Edition User Guide: Compiler .

For information about floorplanning a Partial Reconfiguration design, refer to the Intel® Quartus® Prime Pro Edition User Guide: Partial Reconfiguration .