3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Shadow Register
4.3.3. Arithmetic Logic Unit
4.3.4. Multipy and Divide Units
4.3.5. Floating-Point Unit
4.3.6. Custom Instruction
4.3.7. Instruction Cycles
4.3.8. Reset and Debug Signals
4.3.9. Control and Status Registers
4.3.10. Trap Controller (CLINT)
4.3.11. Trap Controller (CLIC)
4.3.12. Memory and I/O Organization
4.3.13. RISC-V based Debug Module
4.3.14. Error Correction Code (ECC)
4.3.15. Branch Prediction
4.3.16. Lockstep Module
4.3.10.1.1. Machine Status Register (mstatus)
4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.10.1.3. Machine Interrupt Register (mip and mie)
4.3.10.1.4. Machine Exception Program Counter Register (mepc)
4.3.10.1.5. Machine Cause Register (mcause)
4.3.10.1.6. Machine Trap Value Register (mtval)
4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)
4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti)
4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus)
4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh)
4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
4.3.13.3. Program Buffer
Debugger can write small programs into Program Buffer to execute arbitrary instruction, then use Access Register command to initiate the execution (setting command.postexec).
Note that the Nios® V processor Debug Module supports implied ebreak at the non-existent word immediately after the Program Buffer. This saves the debugger from having to write the ebreak itself, and allows the sequence of instructions to be one word smaller.