The value in the each CSR registers determines the state of the Nios® V/m processor. The field descriptions are based on the RISC-V specification.
All CSRs can be accessed by using csrr* instruction in Machine mode except for the Debug mode registers (0x7B0 and 0x7B1) which can only be accessed through Debug mode.
Table 66. Machine Status Register FieldsThe mstatus register is a 32-bit read-write register that keeps track of and controls the hart’s current operating state.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
SD |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
0 |
0 |
MPP[1:0] |
0 |
0 |
MPIE |
0 |
0 |
0 |
MIE |
0 |
0 |
0 |
The following bitfields are read-only 0 because:
- Bit 22 (TSR = 0): S-mode is not supported
- Bit 21 (TW = 0): There are no modes less privileged than M-mode.
- Bit 20 (TVM = 0): S-mode is not supported
- Bit 19 (MXR = 0): S-mode is not supported
- Bit 18 (SUM = 0): S-mode and U-mode are not supported
- Bit 17 (MPRV = 0): U-mode is not supported
- Bit 16 and Bit 15 (XS[1:0] = 0): S-mode is not supported
- Bit 14 and Bit 13 (FS[1:0] = 0): “F” extension for Single-Precision Floating-Point is not supported
- Bit 10 and Bit 9 (VS[1:0] = 0): S-mode is not supported
- Bit 8 (SPP = 0): S-mode is not supported
- Bit 6 (UBE = 0): U-mode is not supported
- Bit 5 (SPIE = 0): S-mode is not supported
- Bit 1 (SIE = 0): S-mode is not supported
Table 67. Machine ISA Register FieldsThe misa CSR is a read-write register reporting the ISA supported by the hart.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
MXL[1:0] |
0 |
Extension[25:0] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Extension[25:0] |
Table 68. Machine Interrupt-Enable Register FieldsThe mie register is a 32-bit read-write register that contains interrupt enable bits. This core does not support supervisor or user modes. Thus, any interrupt related to these modes is read-only 0.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Platform Interrupt[15:0] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
0 |
MEIE |
0 |
0 |
0 |
MTIE |
0 |
0 |
0 |
MSIE |
0 |
0 |
0 |
Table 69. Machine Trap-Handler Base Address Register FieldsThe mtvec register is a 32-bit read/write register that holds trap vector configuration, consisting of a vector base address (BASE) and a vector mode (MODE).
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Base[31:2] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Base[31:2] |
Mode |
Table 70. Machine Exception Program Counter Register FieldsThe mepc register is a 32-bit read-write register that holds the addresses of the instruction that was interrupted or that encountered the exception when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
mepc |
Table 71. Machine Trap Cause Register FieldsThe mcause register is a 32-bit read-write register that hold the code indicating the event that caused the trap when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Interrupt |
Exception code [30:16] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Exception code [15:0] |
Table 72. Machine Trap Value Register Fields The mtval register is a 32-bit read-write register that is written with exception-specific information to assist software in handling the trap when a trap is taken into M-mode.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
mtval |
Table 73. Machine Interrupt-Pending Register FieldsThe mip register is a 32-bit read/write register containing information on pending interrupts. This core does not support supervisor or user modes. Thus, any interrupt related to these modes is read-only 0.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Platform Interrupt[15:0] |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
0 |
MEIP |
0 |
0 |
0 |
MTIP |
0 |
0 |
0 |
MSIP |
0 |
0 |
0 |
Table 74. Trigger Select Register FieldsThe tselect register is a 32-bit read/write register that selects the current trigger is accessible by other trigger register.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
tselect |
Table 75. Trigger Data 1 (Match Control) Register FieldsThe tdata1 (mcontrol) register is a 32-bit read/write register containing information on the trigger type, tdata registers accessibility, and trigger implementation. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
type=2 |
dmode |
maskmax |
hit |
select |
timing |
sizelo |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
action |
chain |
match |
m |
0 |
0 |
0 |
execute |
store |
load |
Table 76. Trigger Data 2 Register FieldsThe tdata2 register is a 32-bit read/write register containing the trigger-specific data.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
… |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
tdata2 |
Table 77. Trigger Info Register FieldsThe tinfo register is a 32-bit read-only register containing information on each possible tdata1.type.
Bit Field |
31 |
30 |
29 |
… |
18 |
17 |
16 |
15 |
14 |
13 |
… |
2 |
1 |
0 |
0 |
info |
Table 78. Debug Control and Status Register FieldsThe dcsr CSR is a 32-bit read-write register containing information and status during D-mode. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
debugver |
0 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
ebreakm |
0 |
0 |
0 |
stepie |
stopcount |
stoptime |
cause |
0 |
mprven |
nmip |
step |
prv |
Table 79. Debug Program Counter Register FieldsUpon entry to D-mode, dpc CSR is updated with the virtual address of the next instruction to be executed.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
dpc |
Table 80. Vendor ID Register FieldsThe mvendorid CSR is a 32-bit read-only register that provides the JEDEC manufacturer ID of the provider of the core.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
Bank |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Bank |
Offset |
Table 81. Architecture ID Register FieldsThe marchid CSR is a 32-bit read-only register encoding the base microarchitecture of the hart.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Architecture ID |
Table 82. Implementation ID Register FieldsThe mimpid CSR provides a unique encoding of the version of the processor implementation.
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Implementation |
Table 83. Hardware Thread ID Register FieldsThe mhartid CSR is a 32-bit read-only register that contains the integer ID of the hardware thread running the code
Bit Field |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
... |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
Hart ID |