Nios® V Processor Reference Manual

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ID 683632
Date 5/25/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Architecture 2.3. Programming Model 2.4. Core Implementation
2.2. Processor Architecture x
2.2.1. General-Purpose Register File 2.2.2. Arithmetic Logic Unit 2.2.3. Reset Signals 2.2.4. Memory and I/O Organization 2.2.5. Error Correction Code (ECC)
2.2.4. Memory and I/O Organization x
2.2.4.1. Instruction and Data Buses 2.2.4.2. Address Map
2.2.4.1. Instruction and Data Buses x
2.2.4.1.1. Instruction Manager Port 2.2.4.1.2. Data Manager Port 2.2.4.1.3. Choosing a Suitable Interface
2.3. Programming Model x
2.3.1. Privilege Levels
2.4. Core Implementation x
2.4.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Instruction Cycles 3.3.6. Trap Controller (CLINT) 3.3.7. Memory and I/O Organization 3.3.8. RISC-V based Debug Module 3.3.9. Error Correction Code (ECC)
3.3.6. Trap Controller (CLINT) x
3.3.6.1. Related Control and Status Register 3.3.6.2. Direct Mode 3.3.6.3. Vectored Mode
3.3.6.1. Related Control and Status Register x
3.3.6.1.1. Machine Status Register (mstatus) 3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec) 3.3.6.1.3. Machine Interrupt Register (mip and mie) 3.3.6.1.4. Machine Exception Program Counter Register (mepc) 3.3.6.1.5. Machine Cause Register (mcause) 3.3.6.1.6. Machine Trap Value Register (mtval)
3.3.6.2. Direct Mode x
3.3.6.2.1. Hardware Implementation 3.3.6.2.2. Software Implementation
3.3.6.3. Vectored Mode x
3.3.6.3.1. Hardware Implementation 3.3.6.3.2. Software Implementation
3.3.7. Memory and I/O Organization x
3.3.7.1. Instruction and Data Buses 3.3.7.2. Address Map
3.3.7.1. Instruction and Data Buses x
3.3.7.1.1. Instruction Manager Port 3.3.7.1.2. Data Manager Port 3.3.7.1.3. Choosing a Suitable Interface
3.3.8. RISC-V based Debug Module x
3.3.8.1. Debug Module 3.3.8.2. Abstract Commands 3.3.8.3. Program Buffer 3.3.8.4. Debug Mode 3.3.8.5. Hardware Trigger Module 3.3.8.6. JTAG Debug Transport Module 3.3.8.7. Nios® V Processor Implementation
3.3.8.1. Debug Module x
3.3.8.1.1. Reset/Halt/Run Control 3.3.8.1.2. Hart States 3.3.8.1.3. Debug Module Register
3.3.8.2. Abstract Commands x
3.3.8.2.1. Access Register Command 3.3.8.2.2. Using Access Register Command
3.3.8.3. Program Buffer x
3.3.8.3.1. Using Program Buffer
3.3.8.4. Debug Mode x
3.3.8.4.1. Enter Debug Mode 3.3.8.4.2. Exit Debug Mode 3.3.8.4.3. Core Debug Registers
3.3.8.5. Hardware Trigger Module x
3.3.8.5.1. Trigger Registers 3.3.8.5.2. Type of Address/Data Match Triggers 3.3.8.5.3. Using Triggers
3.3.8.6. JTAG Debug Transport Module x
3.3.8.6.1. JTAG DTM Registers 3.3.8.6.2. Accessing Debug Module Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field 3.4.2.2. Memory Mapped Registers Fields
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Shadow Register 4.3.3. Arithmetic Logic Unit 4.3.4. Multipy and Divide Units 4.3.5. Floating-Point Unit 4.3.6. Custom Instruction 4.3.7. Instruction Cycles 4.3.8. Reset and Debug Signals 4.3.9. Control and Status Registers 4.3.10. Trap Controller (CLINT) 4.3.11. Trap Controller (CLIC) 4.3.12. Memory and I/O Organization 4.3.13. RISC-V based Debug Module 4.3.14. Error Correction Code (ECC) 4.3.15. Branch Prediction 4.3.16. Lockstep Module
4.3.2. Shadow Register x
4.3.2.1. Shadow Register Implementation 4.3.2.2. Shadow Register Set Management
4.3.2.1. Shadow Register Implementation x
4.3.2.1.1. CLINT 4.3.2.1.2. CLIC with Number of CLIC interrupt levels option 4.3.2.1.3. CLIC with Number of CLIC interrupt levels – 1 Option
4.3.2.2. Shadow Register Set Management x
4.3.2.2.1. Shadow Register File Status CSR (msrfstatus) 4.3.2.2.2. Read Previous Shadow Register CSR (mrdpsrf) 4.3.2.2.3. Write Previous Shadow Register CSR (mwrpsrf)
4.3.5. Floating-Point Unit x
4.3.5.1. IEEE 754 Exception Conditions 4.3.5.2. Floating Point Operations
4.3.5.2. Floating Point Operations x
4.3.5.2.1. Floating Point Classification
4.3.10. Trap Controller (CLINT) x
4.3.10.1. Related Control and Status Register 4.3.10.2. Direct Mode 4.3.10.3. Vectored Mode
4.3.10.1. Related Control and Status Register x
4.3.10.1.1. Machine Status Register (mstatus) 4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec) 4.3.10.1.3. Machine Interrupt Register (mip and mie) 4.3.10.1.4. Machine Exception Program Counter Register (mepc) 4.3.10.1.5. Machine Cause Register (mcause) 4.3.10.1.6. Machine Trap Value Register (mtval) 4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.10.2. Direct Mode x
4.3.10.2.1. Hardware Implementation 4.3.10.2.2. Software Implementation
4.3.10.3. Vectored Mode x
4.3.10.3.1. Hardware Implementation 4.3.10.3.2. Software Implementation
4.3.11. Trap Controller (CLIC) x
4.3.11.1. Related Control and Status Register Fields 4.3.11.2. Hardware Implementation 4.3.11.3. Software Implementation
4.3.11.1. Related Control and Status Register Fields x
4.3.11.1.1. CLIC Registers 4.3.11.1.2. Indirect Access M-mode CSRs 4.3.11.1.3. New M-mode CSRs 4.3.11.1.4. Existing CSRs with Changes 4.3.11.1.5. Existing CSRs without Changes
4.3.11.1.1. CLIC Registers x
4.3.11.1.1.1. CLIC Interrupt Attribute (clicintattr) 4.3.11.1.1.2. CLIC Interrupt Input Control (clicintctl) 4.3.11.1.1.3. CLIC Interrupt Pending (clicintip) 4.3.11.1.1.4. CLIC Interrupt Enable clicintie
4.3.11.1.2. Indirect Access M-mode CSRs x
4.3.11.1.2.1. Packing of Indirectly Accessed CLIC Registers 4.3.11.1.2.2. Read/Write clicintctl[i] and clicintattr[i] 4.3.11.1.2.3. Read/Write clicintip[i] and clicintie[i]
4.3.11.1.3. New M-mode CSRs x
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt) 4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti) 4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus) 4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh) 4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
4.3.11.1.4. Existing CSRs with Changes x
4.3.11.1.4.1. Machine Status Register (mstatus) 4.3.11.1.4.2. Machine Interrupt Register (mie & mip) 4.3.11.1.4.3. Machine Trap-Vector Base-Address Register (mtvec) 4.3.11.1.4.4. Machine Cause Register (mcause)
4.3.11.1.5. Existing CSRs without Changes x
4.3.11.1.5.1. Machine Scratch Register (mscratch) 4.3.11.1.5.2. Machine Exception Program Counter Register (mepc) 4.3.11.1.5.3. Machine Trap Value Register (mtval)
4.3.11.2. Hardware Implementation x
4.3.11.2.1. Asynchronous Interrupt Handling 4.3.11.2.2. Synchronous Exception Handling 4.3.11.2.3. Trap Handling with Pre-emption 4.3.11.2.4. Uninterruptible Critical Section in an Interrupt Handlers 4.3.11.2.5. Returns from Handlers
4.3.11.2.1. Asynchronous Interrupt Handling x
4.3.11.2.1.1. Software-Vectored Interrupt Handling 4.3.11.2.1.2. Hardware-Vectored Interrupt Handling
4.3.12. Memory and I/O Organization x
4.3.12.1. Instruction and Data Buses 4.3.12.2. Address Map 4.3.12.3. Cache Memory 4.3.12.4. Tightly Coupled Memory
4.3.12.1. Instruction and Data Buses x
4.3.12.1.1. Instruction Manager Port 4.3.12.1.2. Data Manager Port
4.3.12.3. Cache Memory x
4.3.12.3.1. Instruction Cache 4.3.12.3.2. Data Cache 4.3.12.3.3. Configurable Cache Memory 4.3.12.3.4. Bypassing Cache (Peripheral Region) 4.3.12.3.5. Using Cache Memory Effectively
4.3.12.4. Tightly Coupled Memory x
4.3.12.4.1. Instruction and Data Tightly Coupled Memory 4.3.12.4.2. Accessing Tightly Coupled Memory 4.3.12.4.3. Using Tightly Coupled Memory Effectively
4.3.13. RISC-V based Debug Module x
4.3.13.1. Debug Module 4.3.13.2. Abstract Commands 4.3.13.3. Program Buffer 4.3.13.4. Debug Mode 4.3.13.5. Hardware Trigger Module 4.3.13.6. JTAG Debug Transport Module 4.3.13.7. Nios® V Processor Implementation
4.3.13.1. Debug Module x
4.3.13.1.1. Reset/Halt/Run Control 4.3.13.1.2. Hart States 4.3.13.1.3. Debug Module Register
4.3.13.2. Abstract Commands x
4.3.13.2.1. Access Register Command 4.3.13.2.2. Using Access Register Command
4.3.13.3. Program Buffer x
4.3.13.3.1. Using Program Buffer
4.3.13.4. Debug Mode x
4.3.13.4.1. Enter Debug Mode 4.3.13.4.2. Exit Debug Mode 4.3.13.4.3. Core Debug Registers
4.3.13.5. Hardware Trigger Module x
4.3.13.5.1. Trigger Registers 4.3.13.5.2. Type of Address/Data Match Triggers 4.3.13.5.3. Using Triggers
4.3.13.6. JTAG Debug Transport Module x
4.3.13.6.1. JTAG DTM Registers 4.3.13.6.2. Accessing Debug Module Interface
4.3.14. Error Correction Code (ECC) x
4.3.14.1. ECC Interface 4.3.14.2. ECC Error Injection 4.3.14.3. Affected CSR during ECC Event
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping (CLINT) 4.4.3. Control and Status Registers (CSR) Mapping (CLIC)
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping (CLINT) x
4.4.2.1. Control and Status Register Field (CLINT) 4.4.2.2. Memory Mapped Registers Fields
4.4.3. Control and Status Registers (CSR) Mapping (CLIC) x
4.4.3.1. Control and Status Register Fields (CLIC) 4.4.3.2. Memory Mapped Registers Fields 4.4.3.3. CLIC Control and Status Registers Fields
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.3.8. Reset and Debug Signals

Interface Type Description
reset Reset A global hardware reset input signal that forces the Nios® V processor to reset immediately.
dbg_reset_out Reset

An optional reset output signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.

  • This reset output signal is triggered by the JTAG debugger or niosv-download -r command.
  • You can connect this reset output signal to the following input signals:
    • To the ndm_reset_in input to reset the core and the timer module.
    • To the reset input signal of other components as needed.
ndm_reset_in Reset

An optional reset input signal which appear after you enable both Enable Debug and Enable Reset from Debug Module parameters.

  • You can use this signal to trigger reset controller to reset the core and the timer module.
  • The reset controller synchronizes the reset (hard reset) and ndm_reset_in signals.
cpu_resetreq Conduit An optional local reset ports which appear after you enable Add Reset Request Interface parameter. The signal consists of an input resetreq signal and an output ack signal that trigger the Nios® V processor to reset without affecting other components in a Nios® V processor system.
  • You can request a reset to the Nios® V processor core by asserting the resetreq signal.
  • The resetreq signal must remain asserted until the processor asserts ack signal. Failure for the signal to remain asserted can cause the processor to be in a non-deterministic state.
  • Assertion of the resetreq signal in debug mode has no effect on the processor's state.
  • The Nios® V processor responds that the reset is successful by asserting the ack signal.
  • After the processor is successfully reset, the assertion of the ack signal can happen multiple times periodically until the de-assertion of the resetreq signal.
Figure 18.  Nios® V/g Processor Reset Network
Level Two Title