Visible to Intel only — GUID: ygi1629681547005
Ixiasoft
3.3.6.1.1. Machine Status Register (mstatus)
3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec)
3.3.6.1.3. Machine Interrupt Register (mip and mie)
3.3.6.1.4. Machine Exception Program Counter Register (mepc)
3.3.6.1.5. Machine Cause Register (mcause)
3.3.6.1.6. Machine Trap Value Register (mtval)
4.3.1. General-Purpose Register File
4.3.2. Shadow Register
4.3.3. Arithmetic Logic Unit
4.3.4. Multipy and Divide Units
4.3.5. Floating-Point Unit
4.3.6. Custom Instruction
4.3.7. Instruction Cycles
4.3.8. Reset and Debug Signals
4.3.9. Control and Status Registers
4.3.10. Trap Controller (CLINT)
4.3.11. Trap Controller (CLIC)
4.3.12. Memory and I/O Organization
4.3.13. RISC-V based Debug Module
4.3.14. Error Correction Code (ECC)
4.3.15. Branch Prediction
4.3.16. Lockstep Module
4.3.10.1.1. Machine Status Register (mstatus)
4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec)
4.3.10.1.3. Machine Interrupt Register (mip and mie)
4.3.10.1.4. Machine Exception Program Counter Register (mepc)
4.3.10.1.5. Machine Cause Register (mcause)
4.3.10.1.6. Machine Trap Value Register (mtval)
4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)
4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti)
4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus)
4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh)
4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
Visible to Intel only — GUID: ygi1629681547005
Ixiasoft
3.5.1. Instruction Set Reference
The Nios® V/m processor is based on the RV32IZicsr specification. RV32IZicsr includes the following instructions sets:
- RV32I base integer instruction set
- Control and status register instructions ("Zicsr" extension).
There are 6 types of instruction formats. They are R-type, I-type, S-type, B-type, U-type, and J-type.
Bit Field (R-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
funct7 | rs2 | rs1 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rs1 | funct3 | rd | opcode |
Bit Field (I-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
imm[11:0] | rs1 | ||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rs1 | funct3 | rd | opcode |
Bit Field (S-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
imm[11:5] | rs2 | rs1 | |||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rs1 | funct3 | imm[4:0] | opcode |
Bit Field (B-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
imm[12] | imm[10:5] | rs2 | rs1 | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
rs1 | funct3 | imm[4:1] | imm[11] | opcode |
Bit Field (U-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
imm[31:16] | |||||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
imm[15:12] | rd | opcode |
Bit Field (J-type) | |||||||||||||||
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
imm[20] | imm[10:1] | imm[11] | imm[19:16] | ||||||||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
imm[15:12] | rd | opcode |
Related Information