Nios® V Processor Reference Manual

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ID 683632
Date 5/25/2025
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Nios® V/c Processor 3. Nios® V/m Processor 4. Nios® V/g Processor 5. Nios V Processor Reference Manual Archives 6. Document Revision History for the Nios® V Processor Reference Manual
1. Overview x
1.1. Quartus® Prime Software Support
2. Nios® V/c Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Architecture 2.3. Programming Model 2.4. Core Implementation
2.2. Processor Architecture x
2.2.1. General-Purpose Register File 2.2.2. Arithmetic Logic Unit 2.2.3. Reset Signals 2.2.4. Memory and I/O Organization 2.2.5. Error Correction Code (ECC)
2.2.4. Memory and I/O Organization x
2.2.4.1. Instruction and Data Buses 2.2.4.2. Address Map
2.2.4.1. Instruction and Data Buses x
2.2.4.1.1. Instruction Manager Port 2.2.4.1.2. Data Manager Port 2.2.4.1.3. Choosing a Suitable Interface
2.3. Programming Model x
2.3.1. Privilege Levels
2.4. Core Implementation x
2.4.1. Instruction Set Reference
3. Nios® V/m Processor x
3.1. Processor Performance Benchmarks 3.2. Processor Pipeline 3.3. Processor Architecture 3.4. Programming Model 3.5. Core Implementation
3.1. Processor Performance Benchmarks x
3.1.1. Pipelined 3.1.2. Non-pipelined
3.2. Processor Pipeline x
3.2.1. Pipelined Architecture 3.2.2. Non-pipelined Architecture
3.3. Processor Architecture x
3.3.1. General-Purpose Register File 3.3.2. Arithmetic Logic Unit 3.3.3. Reset and Debug Signals 3.3.4. Control and Status Registers 3.3.5. Instruction Cycles 3.3.6. Trap Controller (CLINT) 3.3.7. Memory and I/O Organization 3.3.8. RISC-V based Debug Module 3.3.9. Error Correction Code (ECC)
3.3.6. Trap Controller (CLINT) x
3.3.6.1. Related Control and Status Register 3.3.6.2. Direct Mode 3.3.6.3. Vectored Mode
3.3.6.1. Related Control and Status Register x
3.3.6.1.1. Machine Status Register (mstatus) 3.3.6.1.2. Machine Trap-Vector Base-Address Register (mtvec) 3.3.6.1.3. Machine Interrupt Register (mip and mie) 3.3.6.1.4. Machine Exception Program Counter Register (mepc) 3.3.6.1.5. Machine Cause Register (mcause) 3.3.6.1.6. Machine Trap Value Register (mtval)
3.3.6.2. Direct Mode x
3.3.6.2.1. Hardware Implementation 3.3.6.2.2. Software Implementation
3.3.6.3. Vectored Mode x
3.3.6.3.1. Hardware Implementation 3.3.6.3.2. Software Implementation
3.3.7. Memory and I/O Organization x
3.3.7.1. Instruction and Data Buses 3.3.7.2. Address Map
3.3.7.1. Instruction and Data Buses x
3.3.7.1.1. Instruction Manager Port 3.3.7.1.2. Data Manager Port 3.3.7.1.3. Choosing a Suitable Interface
3.3.8. RISC-V based Debug Module x
3.3.8.1. Debug Module 3.3.8.2. Abstract Commands 3.3.8.3. Program Buffer 3.3.8.4. Debug Mode 3.3.8.5. Hardware Trigger Module 3.3.8.6. JTAG Debug Transport Module 3.3.8.7. Nios® V Processor Implementation
3.3.8.1. Debug Module x
3.3.8.1.1. Reset/Halt/Run Control 3.3.8.1.2. Hart States 3.3.8.1.3. Debug Module Register
3.3.8.2. Abstract Commands x
3.3.8.2.1. Access Register Command 3.3.8.2.2. Using Access Register Command
3.3.8.3. Program Buffer x
3.3.8.3.1. Using Program Buffer
3.3.8.4. Debug Mode x
3.3.8.4.1. Enter Debug Mode 3.3.8.4.2. Exit Debug Mode 3.3.8.4.3. Core Debug Registers
3.3.8.5. Hardware Trigger Module x
3.3.8.5.1. Trigger Registers 3.3.8.5.2. Type of Address/Data Match Triggers 3.3.8.5.3. Using Triggers
3.3.8.6. JTAG Debug Transport Module x
3.3.8.6.1. JTAG DTM Registers 3.3.8.6.2. Accessing Debug Module Interface
3.4. Programming Model x
3.4.1. Privilege Levels 3.4.2. Control and Status Registers (CSR) Mapping
3.4.1. Privilege Levels x
3.4.1.1. Machine Mode (M-mode) 3.4.1.2. Debug Mode (D-mode)
3.4.2. Control and Status Registers (CSR) Mapping x
3.4.2.1. Control and Status Register Field 3.4.2.2. Memory Mapped Registers Fields
3.5. Core Implementation x
3.5.1. Instruction Set Reference
4. Nios® V/g Processor x
4.1. Processor Performance Benchmarks 4.2. Processor Pipeline 4.3. Processor Architecture 4.4. Programming Model 4.5. Core Implementation
4.3. Processor Architecture x
4.3.1. General-Purpose Register File 4.3.2. Shadow Register 4.3.3. Arithmetic Logic Unit 4.3.4. Multipy and Divide Units 4.3.5. Floating-Point Unit 4.3.6. Custom Instruction 4.3.7. Instruction Cycles 4.3.8. Reset and Debug Signals 4.3.9. Control and Status Registers 4.3.10. Trap Controller (CLINT) 4.3.11. Trap Controller (CLIC) 4.3.12. Memory and I/O Organization 4.3.13. RISC-V based Debug Module 4.3.14. Error Correction Code (ECC) 4.3.15. Branch Prediction 4.3.16. Lockstep Module
4.3.2. Shadow Register x
4.3.2.1. Shadow Register Implementation 4.3.2.2. Shadow Register Set Management
4.3.2.1. Shadow Register Implementation x
4.3.2.1.1. CLINT 4.3.2.1.2. CLIC with Number of CLIC interrupt levels option 4.3.2.1.3. CLIC with Number of CLIC interrupt levels – 1 Option
4.3.2.2. Shadow Register Set Management x
4.3.2.2.1. Shadow Register File Status CSR (msrfstatus) 4.3.2.2.2. Read Previous Shadow Register CSR (mrdpsrf) 4.3.2.2.3. Write Previous Shadow Register CSR (mwrpsrf)
4.3.5. Floating-Point Unit x
4.3.5.1. IEEE 754 Exception Conditions 4.3.5.2. Floating Point Operations
4.3.5.2. Floating Point Operations x
4.3.5.2.1. Floating Point Classification
4.3.10. Trap Controller (CLINT) x
4.3.10.1. Related Control and Status Register 4.3.10.2. Direct Mode 4.3.10.3. Vectored Mode
4.3.10.1. Related Control and Status Register x
4.3.10.1.1. Machine Status Register (mstatus) 4.3.10.1.2. Machine Trap-Vector Base-Address Register (mtvec) 4.3.10.1.3. Machine Interrupt Register (mip and mie) 4.3.10.1.4. Machine Exception Program Counter Register (mepc) 4.3.10.1.5. Machine Cause Register (mcause) 4.3.10.1.6. Machine Trap Value Register (mtval) 4.3.10.1.7. Machine Second Trap Value Register (mtval2)
4.3.10.2. Direct Mode x
4.3.10.2.1. Hardware Implementation 4.3.10.2.2. Software Implementation
4.3.10.3. Vectored Mode x
4.3.10.3.1. Hardware Implementation 4.3.10.3.2. Software Implementation
4.3.11. Trap Controller (CLIC) x
4.3.11.1. Related Control and Status Register Fields 4.3.11.2. Hardware Implementation 4.3.11.3. Software Implementation
4.3.11.1. Related Control and Status Register Fields x
4.3.11.1.1. CLIC Registers 4.3.11.1.2. Indirect Access M-mode CSRs 4.3.11.1.3. New M-mode CSRs 4.3.11.1.4. Existing CSRs with Changes 4.3.11.1.5. Existing CSRs without Changes
4.3.11.1.1. CLIC Registers x
4.3.11.1.1.1. CLIC Interrupt Attribute (clicintattr) 4.3.11.1.1.2. CLIC Interrupt Input Control (clicintctl) 4.3.11.1.1.3. CLIC Interrupt Pending (clicintip) 4.3.11.1.1.4. CLIC Interrupt Enable clicintie
4.3.11.1.2. Indirect Access M-mode CSRs x
4.3.11.1.2.1. Packing of Indirectly Accessed CLIC Registers 4.3.11.1.2.2. Read/Write clicintctl[i] and clicintattr[i] 4.3.11.1.2.3. Read/Write clicintip[i] and clicintie[i]
4.3.11.1.3. New M-mode CSRs x
4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt) 4.3.11.1.3.2. Machine Next Interrupt Handler Address and Interrupt Enable Register (mnxti) 4.3.11.1.3.3. Machine Interrupt Status Register (mintstatus) 4.3.11.1.3.4. Machine Interrupt-Level Threshold Register (mintthresh) 4.3.11.1.3.5. Machine Scratch Swap for Interrupt-Level Register (mscratchcswl)
4.3.11.1.4. Existing CSRs with Changes x
4.3.11.1.4.1. Machine Status Register (mstatus) 4.3.11.1.4.2. Machine Interrupt Register (mie & mip) 4.3.11.1.4.3. Machine Trap-Vector Base-Address Register (mtvec) 4.3.11.1.4.4. Machine Cause Register (mcause)
4.3.11.1.5. Existing CSRs without Changes x
4.3.11.1.5.1. Machine Scratch Register (mscratch) 4.3.11.1.5.2. Machine Exception Program Counter Register (mepc) 4.3.11.1.5.3. Machine Trap Value Register (mtval)
4.3.11.2. Hardware Implementation x
4.3.11.2.1. Asynchronous Interrupt Handling 4.3.11.2.2. Synchronous Exception Handling 4.3.11.2.3. Trap Handling with Pre-emption 4.3.11.2.4. Uninterruptible Critical Section in an Interrupt Handlers 4.3.11.2.5. Returns from Handlers
4.3.11.2.1. Asynchronous Interrupt Handling x
4.3.11.2.1.1. Software-Vectored Interrupt Handling 4.3.11.2.1.2. Hardware-Vectored Interrupt Handling
4.3.12. Memory and I/O Organization x
4.3.12.1. Instruction and Data Buses 4.3.12.2. Address Map 4.3.12.3. Cache Memory 4.3.12.4. Tightly Coupled Memory
4.3.12.1. Instruction and Data Buses x
4.3.12.1.1. Instruction Manager Port 4.3.12.1.2. Data Manager Port
4.3.12.3. Cache Memory x
4.3.12.3.1. Instruction Cache 4.3.12.3.2. Data Cache 4.3.12.3.3. Configurable Cache Memory 4.3.12.3.4. Bypassing Cache (Peripheral Region) 4.3.12.3.5. Using Cache Memory Effectively
4.3.12.4. Tightly Coupled Memory x
4.3.12.4.1. Instruction and Data Tightly Coupled Memory 4.3.12.4.2. Accessing Tightly Coupled Memory 4.3.12.4.3. Using Tightly Coupled Memory Effectively
4.3.13. RISC-V based Debug Module x
4.3.13.1. Debug Module 4.3.13.2. Abstract Commands 4.3.13.3. Program Buffer 4.3.13.4. Debug Mode 4.3.13.5. Hardware Trigger Module 4.3.13.6. JTAG Debug Transport Module 4.3.13.7. Nios® V Processor Implementation
4.3.13.1. Debug Module x
4.3.13.1.1. Reset/Halt/Run Control 4.3.13.1.2. Hart States 4.3.13.1.3. Debug Module Register
4.3.13.2. Abstract Commands x
4.3.13.2.1. Access Register Command 4.3.13.2.2. Using Access Register Command
4.3.13.3. Program Buffer x
4.3.13.3.1. Using Program Buffer
4.3.13.4. Debug Mode x
4.3.13.4.1. Enter Debug Mode 4.3.13.4.2. Exit Debug Mode 4.3.13.4.3. Core Debug Registers
4.3.13.5. Hardware Trigger Module x
4.3.13.5.1. Trigger Registers 4.3.13.5.2. Type of Address/Data Match Triggers 4.3.13.5.3. Using Triggers
4.3.13.6. JTAG Debug Transport Module x
4.3.13.6.1. JTAG DTM Registers 4.3.13.6.2. Accessing Debug Module Interface
4.3.14. Error Correction Code (ECC) x
4.3.14.1. ECC Interface 4.3.14.2. ECC Error Injection 4.3.14.3. Affected CSR during ECC Event
4.4. Programming Model x
4.4.1. Privilege Levels 4.4.2. Control and Status Registers (CSR) Mapping (CLINT) 4.4.3. Control and Status Registers (CSR) Mapping (CLIC)
4.4.1. Privilege Levels x
4.4.1.1. Machine Mode (M-mode) 4.4.1.2. Debug Mode (D-mode)
4.4.2. Control and Status Registers (CSR) Mapping (CLINT) x
4.4.2.1. Control and Status Register Field (CLINT) 4.4.2.2. Memory Mapped Registers Fields
4.4.3. Control and Status Registers (CSR) Mapping (CLIC) x
4.4.3.1. Control and Status Register Fields (CLIC) 4.4.3.2. Memory Mapped Registers Fields 4.4.3.3. CLIC Control and Status Registers Fields
4.5. Core Implementation x
4.5.1. Instruction Set Reference
1. Overview
2. Nios® V/c Processor
3. Nios® V/m Processor
4. Nios® V/g Processor
5. Nios V Processor Reference Manual Archives
6. Document Revision History for the Nios® V Processor Reference Manual

4.4.3.1. Control and Status Register Fields (CLIC)

The value in each CSR registers determines the state of the Nios® V/g processor. The field descriptions are based on the RISC-V specification. You can access all CSRs by using csrr* instruction in Machine mode except for the Debug mode registers (0x7B0 and 0x7B1) which can only be accessed through Debug mode.

Table 207.  Floating-Point CSR Register FieldsThe fcsr CSR is a 32-bit read/write register that holds the accrued exception flags.

RISC-V CSR instructions can access fflags and frm field individually by specifying the CSR address (0x001 and 0x002) respectively.

When accessing frm field individually using the CSR address 0x002, the rounding mode is transferred as bits [2:0] of the destination register.

RNE (000) is the only supporting rounding mode. Writing other rounding mode into frm generates an illegal instruction exception.

Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved

Rounding Mode

(frm)

Accured Exceptions

(fflags)

000 NV DZ OF UF NX
Table 208.  Machine Status Register FieldsThe mstatus register is a 32-bit read-write register that keeps track of and controls the hart’s current operating state.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SD 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 FS[1:0] MPP[1:0] 0 0 MPIE 0 0 0 MIE 0 0 0

The following bitfields are read-only 0:

  • Bit 22 (TSR = 0): S-mode is not supported
  • Bit 21 (TW = 0): There are no modes less privileged than M-mode.
  • Bit 20 (TVM = 0): S-mode is not supported
  • Bit 19 (MXR = 0): S-mode is not supported
  • Bit 18 (SUM = 0): S-mode and U-mode are not supported
  • Bit 17 (MPRV = 0): U-mode is not supported
  • Bit 16 and Bit 15 (XS[1:0] = 0): S-mode is not supported
  • Bit 10 and Bit 9 (VS[1:0] = 0): S-mode is not supported
  • Bit 8 (SPP = 0): S-mode is not supported
  • Bit 6 (UBE = 0): U-mode is not supported
  • Bit 5 (SPIE = 0): S-mode is not supported
  • Bit 1 (SIE = 0): S-mode is not supported
Table 209.  Machine ISA Register FieldsThe misa CSR is a read-write register reporting the ISA supported by the hart.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MXL[1:0] 0 Extension[25:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Extension[25:0] .
Table 210.  Machine Interrupt-Enable Register FieldsThe mie register is a 32-bit read-write register that contains interrupt enable bits. In CLIC mode, the mie register is inactive, thus hardwired to 0. It is replaced by the CLIC interrupt enable register (clicintie)
Bit Field
31 … 0
0
Table 211.  Machine Trap-Handler Base Address Register Fields (For CLIC mode)The mtvec register is a 32-bit read/write register that holds trap CLIC configuration, consisting of a trap CLIC base address (base) and a CLIC mode (mode = 11). submode bit field is reserved for future use.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
base[31:6]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
base[31:6] submode = 0 mode = 11
Table 212.  Machine Trap-Handler Vector Table Base Address Register FieldsThe mtvt register is a 32-bit read-write register that holds the Machine Trap Vector base address for CLIC vectored interrupts.
Bit Field
31 30 29 … 8 7 6 5 4 3 2 1 0
base[31:6] Reserved.
Table 213.  Machine Scratch Register for Trap Handler Register FieldsThe mscratch register is a 32-bit read-write register that holds a pointer to a machine-mode hart-local context space and swapped with a user register upon entry to an M-mode trap handler.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mscratch
Table 214.  Machine Exception Program Counter Register FieldsThe mepc register is a 32-bit read-write register that holds the addresses of the instruction that was interrupted or that encountered the exception when a trap is taken into M-mode.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mepc
Table 215.  Machine Trap Cause Register Fields (For CLIC mode)The mcause register is a 32-bit read-write register that holds the code indicating the event that caused the trap when a trap is taken into M-mode.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
interrupt minhv mpp[1:0] = 00 mpie Reserved mpil[7:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved exccode[11:0]
Table 216.  Machine Trap Value Register FieldsThe mtval register is a 32-bit read-write register that is written with exception-specific information to assist software in handling the trap.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mtval
Table 217.  Machine Interrupt-Pending Register FieldsThe mip register is a 32-bit read/write register containing information on pending interrupts. In CLIC mode, the mip register is inactive, thus hardwired to 0. It is replaced by separate interrupt pending (clicintip).
Bit Field
31 … 0
0
Table 218.  Machine Next Interrupt Handler Address and Interrupt Enable Register FieldThe mnxti register is a 32-bit read-write register that improve the performance of handling back-to-back software vectored interrupts.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mnxti
Table 219.  Machine Interrupt-Level Register FieldsThe mintthresh register is a 32-bit read-write register that holds an 8-bit field for the threshold level.
Bit Field
31 30 29 … 9 8 7 6 5 4 3 2 1 0
Reserved = 0 threshold
Table 220.  Machine Scratch Swap for Interrupt-Level Change Register FieldsThe mscratchswl register is a 32-bit read-write register that support faster swapping of the stack pointer between interrupt and non-interrupt code.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mscratchswl
Table 221.  Machine Interrupt Status Register FieldsThe mintstatus register is a 32-bit read-write register that holds the active interrupt level.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
mil Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Reserved
Table 222.  Machine Indirect Select Register FieldsThe miselect register is a 32-bit read-write register that select the CLIC registers based on specific index.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
miselect
Table 223.  Machine Indirect Alias Register FieldsThe mireg register is a 32-bit read-write register that hold the current value of the CLIC register for register read and write operation. Use miselect register to select which CLIC register to display. Refer to Packing of Indirectly Accessed CLIC Registers for more information.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mireg
Table 224.  Machine Indirect Alias 2 Register FieldsThe mireg2 register is a 32-bit read-write register that hold the current value of the CLIC register for register read and write operation. Use miselect register to select which CLIC register to display. Refer to Packing of Indirectly Accessed CLIC Registers for more information.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mireg2
Table 225.  Trigger Select Register FieldsThe tselect register is a 32-bit read/write register that selects the current trigger is accessible by other trigger register.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
tselect
Table 226.  Trigger Data 1 (Match Control) Register FieldsThe tdata1 (mcontrol) register is a 32-bit read/write register containing information on the trigger type, tdata registers accessibility, and trigger implementation. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
type = 2 dmode maskmax hit select timing sizelo
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
action chain match m 0 0 0 execute store load
Table 227.  Trigger Data 2 Register FieldsThe tdata2 register is a 32-bit read/write register containing the trigger-specific data.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
tdata2
Table 228.  Trigger Info Register FieldsThe tinfo register is a 32-bit read-only register containing information on each possible tdata1.type.
Bit Field
31 30 29 … 18 17 16 15 14 13 … 2 1 0
0 info
Table 229.  Debug Control and Status Register FieldsThe dcsr CSR is a 32-bit read-write register containing information and status during D-mode. This core does not support supervisor or user modes. Thus, any bitfield related to these modes is read-only 0.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
debugver 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ebreakm 0 0 0 stepie stopcount stoptime cause 0 mprven nmip step Prv
Table 230.  Debug Program Counter Register FieldsUpon entry to D-mode, dpc CSR is updated with the virtual address of the next instruction to be executed.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
dpc
Table 231.  Shadow Register File Status CSR FieldsThe msrfstatus is a 32-bits wide register containing shadow register status information. Refer to Shadow Registerr for more information.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ESI Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
psrf asrf
Table 232.  Read Previous Shadow Register CSR FieldsThe m rdpsrf register facilitates copying a single register from previous shadow register sets to the active one. Refer to Shadow Register for more information.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mrdpsrf
Table 233.  Write Previous Shadow Register CSR FieldsThe mwrpsrf register facilitates copying a single register from active shadow register sets to the previous one. Refer to 4.3.2. Shadow Register for more information.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
mwrpsrf
Table 234.  Vendor ID Register FieldsThe mvendorid CSR is a 32-bit read-only register that provides the JEDEC manufacturer ID of the provider of the core.
Bit Field
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Bank
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bank Offset
Table 235.  Architecture ID Register FieldsThe marchid CSR is a 32-bit read-only register encoding the base microarchitecture of the hart.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
Architecture ID
Table 236.  Implementation ID Register FieldsThe mimpid CSR provides a unique encoding of the version of the processor implementation.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
Implementation
Table 237.  Hardware Thread ID Register FieldsThe mhartid CSR is a 32-bit read-only register that contains the integer ID of the hardware thread running the code.
Bit Field
31 30 29 28 27 26 25 … 6 5 4 3 2 1 0
Hart ID
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