Visible to Intel only — GUID: lni1629599579873
Ixiasoft
Visible to Intel only — GUID: lni1629599579873
Ixiasoft
3.3.7.1.1. Instruction Manager Port
Nios® V/m processor instruction bus is implemented as a 32-bit AMBA* 4 AXI-Lite manager port as default interface. You can switch it to Avalon® memory-mapped interface for smaller logic utilization.
- Performs a single function: it fetches instructions to be executed by the processor.
- Does not perform any write operations.
- Can issue successive read requests before data return from prior requests.
- Can prefetch sequential instructions.
- Always retrieves 32-bit of data. Every instruction fetch returns a full instruction word, regardless of the width of the target memory. The widths of memory in the Nios® V/m processor system is not applicable to the programs. Instruction address is always aligned to a 32-bit word boundary.
- Does not require any burst adapter because it is non-bursting.
Interface | Signal | Role | Width | Direction |
---|---|---|---|---|
Write Address Channel | awaddr | Unused | [31:0] | Output |
awprot | Unused | [2:0] | Output | |
awvalid | Unused | 1 | Output | |
awready | Unused | 1 | Input | |
Write Data Channel | wdata | Unused | [31:0] | Output |
wstrb | Unused | [3:0] | Output | |
wvalid | Unused | 1 | Output | |
wready | Unused | 1 | Input | |
Write Response Channel | bresp | Unused | [1:0] | Input |
bvalid | Unused | 1 | Input | |
bready | Unused | 1 | Output | |
Read Address Channel | araddr | Instruction Address (Program Counter) |
[31:0] | Output |
arprot | Unused | [2:0] | Output | |
arvalid | Instruction address valid | 1 | Output | |
arready | Instruction address ready (from memory) |
1 | Input | |
Read Data Channel | rdata | Instruction | [31:0] | Input |
rresp | Instruction response: Non-zero value denotes instruction access fault exception | [1:0] | Input | |
rvalid | Instruction valid | 1 | Input | |
rready | Constant 1 | 1 | Output |
Signal | Role | Width | Direction |
---|---|---|---|
readdata | Instruction | [31:0] | Agent → Processor |
waitrequest | Force the processor to wait until the agent is ready | 1 | Agent → Processor |
readdatavalid | Instruction is valid | 1 | Agent → Processor |
response | Instruction response: Non-zero value denotes instruction access fault exception | [31:0] | Agent → Processor |
address | Instruction Address (Program Counter) |
[31:0] | Processor → Agent |
read | Asserted to indicate a read transfer. | 1 | Processor → Agent |