Nios® V Processor Reference Manual

ID 683632
Date 5/25/2025
Public

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Ixiasoft

Document Table of Contents

4.3.11.1.3.1. Machine Trap-handler Vector Table base address Register (mtvt)

The mtvt 32-bit CSR holds the base address of the trap vector table, aligned on a 64-byte or greater power-of-two boundary. The actual alignment can be determined by writing ones to the low-order bits then reading them back. Values other than 0 in the low 6 bits of mtvt are reserved.

The value of the mtvt CSR is provided when the mnxti CSR is read.

Table 127.   mtvt register layout
31 6 5 0
base[31:6] Reserved