AN 883: Intel Arria 10 DisplayPort TX-only Design

ID 683597
Date 7/03/2021

1.5.4. Generated Clocks

Apart from the default clocking scheme in the generated design example, you need to generate an additional output clock from the video PLL. To do that, double click on video_pll_a10.ip on Quartus Project Navigator to open IP Parameter Editor.
Table 8.  DisplayPort TX-only Design Generated Clocks
Clocks Signal Name Description
outclk_0 (default) vip_clk 160 MHz output clock that acts as the main clock for CVO II and TPG II FPGA IP instances through VIP Clock Bridge.
outclk_1 (default) clk_16 16 MHz output clock for DisplayPort Source 1 Mbps AUX channel interface.
outclk_2 (user-generated) tx_vid_clk 148.5 MHz output clock for DisplayPort TX and CVO II video clocks.
Note: The 148.5 MHz clock frequency supports the native 4K or UHD resolution video output. Other video formats may run at different clock frequency.
After you make the changes, click Save and Generate HDL.

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