AN 883: Intel Arria 10 DisplayPort TX-only Design

ID 683597
Date 7/03/2021

1.2. Clocking Scheme

The clocking scheme illustrates the clock domains in the DisplayPort Intel® FPGA IP core design example.
Table 4.  Clocking Scheme Signals
Clock Signal Name in Design Description
TX PLL Refclock tx_pll_refclk

135 MHz TX PLL reference clock, that is divisible by the transceiver for all DisplayPort data rates (1.62 Gbps, 2.7 Gbps, and 5.4 Gbps).

Note: The reference clock source of the TX PLL refclock is located at the HSSI refclk pin.
TX Transceiver Clockout gxb_tx_clkout

TX clock recovered from the transceiver, and the frequency varies depending on the data rate and symbols per clock.

Data Rate Symbols per Clock Frequency (MHz)

RBR (1.62 Gbps)

2 (dual)

4 (quad) 40.5

HBR (2.7 Gbps)

2 (dual) 135
4 (quad) 62.5

HBR2 (5.4 Gbps)

2 (dual) 270
4 (quad) 135
HBR3 (8.1 Gbps) 4 (quad) 202.5
Management Clock


A free running 100 MHz clock for both Avalon-MM interfaces for reconfiguration and PHY reset controller for transceiver reset sequence.

Component Required Frequency (MHz)
Avalon-MM reconfiguration 100 – 125
Transceiver PHY reset controller 1 – 500
16 MHz Clock clk_16

16 MHz clock used to encode and decode auxiliary channel in the DisplayPort Intel® FPGA source and sink IP cores.

Calibration Clock


A 50 MHz calibration clock input that must be synchronous to the Transceiver Reconfiguration module's clock. This clock is used in the DisplayPort Intel® FPGA IP core's reconfiguration logic.

TX Video Clock tx_vid_clk

Video clock frequency generated from IOPLL. A correct output clock frequency needs to be generated according to video format.

Used when DisplayPort source's TX_SUPPORT_IM_ENABLE = 0.

CVO Video Clock tx_vid_clk Fixed video clock generated by the video PLL (148.5 MHz) to the DisplayPort Intel® FPGA source.
VIP Clock vip_clk 160 MHz clock generated by the video PLL.

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