AN 883: Intel Arria 10 DisplayPort TX-only Design

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ID 683597
Date 7/03/2021
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® 10 DisplayPort TX-only Design
1. Intel® Arria® 10 DisplayPort TX-only Design x
1.1. Design Components 1.2. Clocking Scheme 1.3. Top Level Interface Signals 1.4. Quick Start Guide 1.5. Creating the TX-only Design with Bitec FMC Daughter Card 1.6. Document Revision History for AN 883: Intel Arria 10 DisplayPort TX-only Design
1.4. Quick Start Guide x
1.4.1. Hardware and Software Requirements 1.4.2. Compiling and Testing the Design 1.4.3. Running the Hardware 1.4.4. Design Debug Features
1.4.2. Compiling and Testing the Design x
1.4.2.1. Regenerating ELF File
1.4.4. Design Debug Features x
1.4.4.1. Main Stream Attribute (MSA) Information 1.4.4.2. Auxiliary Channel Traffic Monitor
1.5. Creating the TX-only Design with Bitec FMC Daughter Card x
1.5.1. Generating the Design 1.5.2. Removing Irrelevant Blocks 1.5.3. Instantiating Video and Image Processing (VIP) Intel® FPGA IPs 1.5.4. Generated Clocks 1.5.5. Making a Direct Connection to the TX Transceiver Block 1.5.6. Modifying the Software
1.5.2. Removing Irrelevant Blocks x
1.5.2.1. Removing Irrelevant Block in Top Level Example Design a10_dp_demo.v File 1.5.2.2. Removing Irrelevant Block in Platform Designer
1. Intel® Arria® 10 DisplayPort TX-only Design

1.5.5. Making a Direct Connection to the TX Transceiver Block

The existing dynamic DisplayPort parallel SST loopback with PCR design example uses the Transceiver Arbiter to share between an RX and TX transceiver within the same channel. As the TX-only design only requires the TX transceiver, you need to remove the Transceiver Arbiter and make a direct connection to the TX transceiver.
  1. Before you make the connection, in the Platform Designer turn on the Share Reconfiguration Interface parameter in the Transceiver Native PHY block to allow for single Avalon-MM slave interface for dynamic reconfiguration of all channels.
  2. Update the transceiver signal width as shown below in the design top-level and the tx_phy_top.v files.
    Table 9.  TX Transceiver Signals
    Signal Direction Width (Bit)
    gxb_tx_rcfg_write Input 1
    gxb_tx_rcfg_read Input 1
    gxb_tx_rcfg_address Input 12
    gxb_tx_rcfg_writedata Input 32
    gxb_tx_rcfg_readdata Input 32
    gxb_tx_rcfg_waitrequest Input 1
  3. Make a direct connection from the Bitec Reconfig block to the TX transceiver block in the tx_phy_top.v file as shown in the diagram below.
    Figure 8. Bitec Reconfig and TX Transceiver Block Connection
  4. Remove the following Transceiver Reconfig Group assignments from the Intel® Quartus® Prime Settings File (qsf).
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 1 -to fmca_dp_c2m_p[0] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 2 -to fmca_dp_c2m_p[1] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 3 -to fmca_dp_c2m_p[2] -entity a10_dp_demo
    • - set_instance_assignment -name XCVR_RECONFIG_GROUP 4 -to fmca_dp_c2m_p[3] -entity a10_dp_demo
Level Two Title